关于Pipeline ADC的SFDR 低于0dB
时间：10-02
整理：3721RD
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各位大神看下，一般我们做ADC的SFDR分析时，在输入信号处，其值一般都为0dB左右是吧?为什么我的在输入信号频率处只有-25dB呢?求指教啊?
那信号频率处应该是多少
请问用ADC怎么做SFDR测试啊?
基频都看不到?
I think this has problem with choosing input frequency
Use clean sinewave as input, use low jitter clock. Use logic analyzer get digital signal, take sevral signal cycle (complete cycles). Use Matlab analysis, you can take window. Then FFT, plot in dB, the dB value between main signal & maximum tone is the SFDR.
sim by matlab ！