急！求助高手，synplify的综合问题

大家帮我看下这段代码，risc的顶层模块，synplify综合是总报warning “input clk，rst is unused”。我检查了很多次，clk，rst都用到了啊
module risc_spm(clk,rst);
  parameter wordsize=8;
  parameter sel1_size=3;
  parameter sel2_size=2;
  input     clk,rst;
  wire      [sel1_size-1:0] sel_bus_1_mux;
  wire      [sel2_size-1:0] sel_bus_2_mux;
  //data wire
  wire      clk,rst;
  wire      zero;
  wire      [wordsize-1:0]  instruction,address,bus_1,mem_word;
  //control wire
  wire      load_r0,load_r1,load_r2,load_r3,load_pc,inc_pc,load_ir;
  wire      load_add_r,load_reg_y,load_reg_z;
  wire      write;

  processing_unit M0_processor(.instruction(instruction),.zflag(zero),.address(address),.bus_1(bus_1),.mem_word(mem_word),
                               .load_r0(load_r0),.load_r1(load_r1),.load_r2(load_r2),.load_r3(load_r3),.load_pc(load_pc),.inc_pc(inc_pc),.sel_bus_1_mux(sel_bus_1_mux),
                               .load_ir(load_ir),.load_add_r(load_add_r),.load_reg_y(load_reg_y),.load_reg_z(load_reg_z),
                               .sel_bus_2_mux(sel_bus_2_mux),.clk(clk),.rst(rst));

  control_unit    M1_controller(.load_r0(load_r0),.load_r1(load_r1),.load_r2(load_r2),.load_r3(load_r3),
                                .load_pc(load_pc),.inc_pc(inc_pc),
                                .sel_bus_1_mux(sel_bus_1_mux),.sel_bus_2_mux(sel_bus_2_mux),
                                .load_ir(load_ir),.load_add_r(load_add_r),.load_reg_y(load_reg_y),.load_reg_z(load_reg_z),
                                .write(write),.instruction(instruction),.zero(zero),.clk(clk),.rst(rst));
  memory_unit     M2_SRAM       (.data_out(mem_word),.data_in(bus_1),.address(address),.clk(clk),.write(write));
endmodule

I don't see any output in your module. In that case, most synthesis tools will optimize away all internal logics.

模块没有输出逻辑，因此被综合掉了

郁闷  又没有信元了。