Ncverilog 仿RTL code时 加unit Delay
时间：10-02
整理：3721RD
点击：
ex：wire a, b;
assign b = a;
怎样能看到b 和a timing difference
ex：
input [7:0] addr;
input clk;
reg [7:0] addr_syn;
always @ (posedge clk)
addr_syn <= addr;
怎样能看到 addr_syn 的delay?
assign b = a;
怎样能看到b 和a timing difference
ex：
input [7:0] addr;
input clk;
reg [7:0] addr_syn;
always @ (posedge clk)
addr_syn <= addr;
怎样能看到 addr_syn 的delay?
求助......