关于数字设计的几道选择题，帮帮忙拉．
时间：10-02
整理：3721RD
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Good Quality Design
问题1. A not-well designed feedback circuit may cause
a)transition time problem in a logic device
b) race condition
c)timing hazard
d)clock skew
e)metastable behavior
问题2. Unreliable clock configuration may produce problems in set-up and hold times.
a)True
b) False
c)Maybe
d)It depends
e)It's hard to tell
问题3. Unreliable clock configuration may produce problems in transition times of a device.
a) True
b) False
c) Maybe
d)It depends
e) It's hard to tell
问题4. In the design of a synchronous system in a PLD or FPGA, clock skew may result when clock signals are not connected to global clocks.
a)True
b) False
c)Maybe
d)It depends
e) It's hard to tell
问题5. In the design of a synchronous system, asynchronous reset is preferred over synchronous reset.
a)True
b)Implementation of asynchronous reset is recommended only in asynchronous system design
c)Both reset configurations can be interchangeably and simultaneously used within the system
d)Synchronous reset is preferred over asynchronous reset.
e)None of the above
问题6. Multiple clock network configuration may cause
a)transition time problem in a logic device
b)race condition
c)timing hazard
d)metastable behavior
e)none of the above
问题7. Timing hazards can be eliminated using
a)XOR gate
b)amplifier
c)mux
d)dffs
e)None of the above
问题8. In the design of a synchronous system, it is advisable to use only clocks that are connected to the global clocks within the PLD or FPGA devices to avoid unreliable timing results.
a)The above statement is true
b)Timing is not affected by clock configuration.
c)Unreliable timing results only in the use of ripple clock
d)PLD and FPGA devices have no global clocks
e)None of the above
问题9. Design of clock and reset circuits should be as simple as possible, and should be in a separate block or module.
a)True
b)False
c)Maybe
d)Sometimes
e)It doesn't matter
问题10. Asynchronous inputs may cause metastability behavior.
a) True
b) False
c)Maybe
d) Sometimes
e) It doesn't matter
问题1. A not-well designed feedback circuit may cause
a)transition time problem in a logic device
b) race condition
c)timing hazard
d)clock skew
e)metastable behavior
问题2. Unreliable clock configuration may produce problems in set-up and hold times.
a)True
b) False
c)Maybe
d)It depends
e)It's hard to tell
问题3. Unreliable clock configuration may produce problems in transition times of a device.
a) True
b) False
c) Maybe
d)It depends
e) It's hard to tell
问题4. In the design of a synchronous system in a PLD or FPGA, clock skew may result when clock signals are not connected to global clocks.
a)True
b) False
c)Maybe
d)It depends
e) It's hard to tell
问题5. In the design of a synchronous system, asynchronous reset is preferred over synchronous reset.
a)True
b)Implementation of asynchronous reset is recommended only in asynchronous system design
c)Both reset configurations can be interchangeably and simultaneously used within the system
d)Synchronous reset is preferred over asynchronous reset.
e)None of the above
问题6. Multiple clock network configuration may cause
a)transition time problem in a logic device
b)race condition
c)timing hazard
d)metastable behavior
e)none of the above
问题7. Timing hazards can be eliminated using
a)XOR gate
b)amplifier
c)mux
d)dffs
e)None of the above
问题8. In the design of a synchronous system, it is advisable to use only clocks that are connected to the global clocks within the PLD or FPGA devices to avoid unreliable timing results.
a)The above statement is true
b)Timing is not affected by clock configuration.
c)Unreliable timing results only in the use of ripple clock
d)PLD and FPGA devices have no global clocks
e)None of the above
问题9. Design of clock and reset circuits should be as simple as possible, and should be in a separate block or module.
a)True
b)False
c)Maybe
d)Sometimes
e)It doesn't matter
问题10. Asynchronous inputs may cause metastability behavior.
a) True
b) False
c)Maybe
d) Sometimes
e) It doesn't matter
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