Xcelium 编译xilinx库错误

编译库的时候发现serdes的加密文件编译过不去
换成ies 和vcs就不会报错了。大家有遇到过这个问题么?

file: /home/soft/Xilinx/Vivado/2018.3/data/secureip/gthe3_channel/gthe3_channel_001.vp
xmvlog: *F,INTERR: INTERNAL EXCEPTION
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contAIns this error message.
TOOL:xmvlog(64)18.03-s001
HOSTNAME: roc.nb.centos7
OPERATING SYSTEM: Linux 3.10.0-957.12.1.el7.x86_64 #1 SMP Mon Apr 29 14:59:59 UTC 2019 x86_64
MESSAGE: dt_get_known_datatype hit unknown datatype
-----------------------------------------------------------------
csi-xmvlog - CSI: Cadence Support Investigation, sending details to /home/roc/xmvlog_28733.err
csi-xmvlog - CSI: investigation complete, send /home/roc/xmvlog_28733.err to Cadence Support
xmvlog(64): 18.03-s001: (c) Copyright 1995-2018 Cadence Design Systems, Inc.


csi-xmvlog - CSI: Command line:
/home/soft/cadence/XCELIUM1803/tools/bin/64bit/xmvlog
-MESSAGES
-NOLOG
-CDSLIB cds.lib
-hdlVAR hdl.var
-work secureip
-f /home/roc/xil_simlib/xcelium_2018.3/secureip/.cxl.verilog.secureip.secureip.lin64.cmf
/home/soft/Xilinx/Vivado/2018.3/data/secureip/hbm_one_stack_intf/hbm_one_stack_intf_001.sv
/home/soft/Xilinx/Vivado/2018.3/data/secureip/hbm_two_stack_intf/hbm_two_stack_intf_001.sv
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gthe2_channel_fast/gthe2_channel_fast_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gthe2_channel_fast/gthe2_channel_fast_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gtxe2_channel_fast/gtxe2_channel_fast_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gtxe2_channel_fast/gtxe2_channel_fast_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gtxe2_channel/gtxe2_channel_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gtxe2_channel/gtxe2_channel_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gtxe2_common/gtxe2_common_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gtxe2_common/gtxe2_common_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/pcie_2_1/pcie_2_1_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/pcie_2_1/pcie_2_1_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/iserdese2/iserdese2_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/iserdese2/iserdese2_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/oserdese2/oserdese2_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/oserdese2/oserdese2_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/in_fifo/in_fifo_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/in_fifo/in_fifo_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/out_fifo/out_fifo_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/out_fifo/out_fifo_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/phy_control/phy_control_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/phy_control/phy_control_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/phaser_in/phaser_in_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/phaser_in/phaser_in_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/phaser_out/phaser_out_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/phaser_out/phaser_out_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gthe2_channel/gthe2_channel_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gthe2_channel/gthe2_channel_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gthe2_common/gthe2_common_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gthe2_common/gthe2_common_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/pcie_3_0/pcie_3_0_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/pcie_3_0/pcie_3_0_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gtpe2_channel/gtpe2_channel_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gtpe2_channel/gtpe2_channel_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gtpe2_common/gtpe2_common_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gtpe2_common/gtpe2_common_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gthe3_channel/gthe3_channel_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gthe3_channel/gthe3_channel_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gthe3_common/gthe3_common_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gthe3_common/gthe3_common_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gtye3_channel/gtye3_channel_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gtye3_channel/gtye3_channel_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gtye3_common/gtye3_common_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gtye3_common/gtye3_common_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/iserdese3/iserdese3_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/iserdese3/iserdese3_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/oserdese3_k2/oserdese3_k2_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/oserdese3_k2/oserdese3_k2_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/rxtx_bitslice_k2/rxtx_bitslice_k2_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/rxtx_bitslice_k2/rxtx_bitslice_k2_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/rx_bitslice_k2/rx_bitslice_k2_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/rx_bitslice_k2/rx_bitslice_k2_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/tx_bitslice_k2/tx_bitslice_k2_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/tx_bitslice_k2/tx_bitslice_k2_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/tx_bitslice_tri_k2/tx_bitslice_tri_k2_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/tx_bitslice_tri_k2/tx_bitslice_tri_k2_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/bitslice_control_k2/bitslice_control_k2_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/bitslice_control_k2/bitslice_control_k2_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/iserdese3_d1/iserdese3_d1_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/iserdese3_d1/iserdese3_d1_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/oserdese3_d1/oserdese3_d1_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/oserdese3_d1/oserdese3_d1_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/rxtx_bitslice_d1/rxtx_bitslice_d1_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/rxtx_bitslice_d1/rxtx_bitslice_d1_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/rx_bitslice_d1/rx_bitslice_d1_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/rx_bitslice_d1/rx_bitslice_d1_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/tx_bitslice_d1/tx_bitslice_d1_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/tx_bitslice_d1/tx_bitslice_d1_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/tx_bitslice_tri_d1/tx_bitslice_tri_d1_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/tx_bitslice_tri_d1/tx_bitslice_tri_d1_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/bitslice_control_d1/bitslice_control_d1_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/bitslice_control_d1/bitslice_control_d1_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/pcie_3_1/pcie_3_1_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/pcie_3_1/pcie_3_1_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/cmac/cmac_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/cmac/cmac_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/cmac_es2/cmac_es2_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/cmac_es2/cmac_es2_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/ilkn/ilkn_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/ilkn/ilkn_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/ilkn_es2/ilkn_es2_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/ilkn_es2/ilkn_es2_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/cmace4/cmace4_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/cmace4/cmace4_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gthe4_channel/gthe4_channel_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gthe4_channel/gthe4_channel_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gthe4_common/gthe4_common_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gthe4_common/gthe4_common_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gtye4_channel/gtye4_channel_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gtye4_channel/gtye4_channel_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gtye4_common/gtye4_common_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/gtye4_common/gtye4_common_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/ilkne4/ilkne4_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/ilkne4/ilkne4_002.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/pcie40e4/pcie40e4_001.vp
/home/soft/Xilinx/Vivado/2018.3/data/secureip/pcie40e4/pcie40e4_002.vp
csi-xmvlog - CSI: *F,INTERR: INTERNAL EXCEPTION
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
TOOL:xmvlog(64)18.03-s001
HOSTNAME: roc.nb.centos7
OPERATING SYSTEM: Linux 3.10.0-957.12.1.el7.x86_64 #1 SMP Mon Apr 29 14:59:59 UTC 2019 x86_64
MESSAGE: dt_get_known_datatype hit unknown datatype
-----------------------------------------------------------------
csi-xmvlog - CSI: Cadence Support Investigation, recording details
Verilog Syntax Tree: module declaration (VST_D_MODULE)
File: /home/soft/Xilinx/Vivado/2018.3/data/secureip/gthe3_channel/gthe3_channel_001.vp, line 29, position 23
Scope: SIP_GTHE3_CHANNEL
Decompile: SIP_GTHE3_CHANNEL#(SIM_RECEIVER_DETECT_PASS,SIM_RESET_SPEEDUP,SIM_TX_EIDLE_DRIVE_LEVEL,SIM_VERSION,clock_delay,data_delay,enable_delay,reset_delay,setreset_delay)
Source: module SIP_GTHE3_CHANNEL #(
Position:^
Verilog Syntax Tree: always statement declaration (VST_D_ALWAYS_STMT)
Scope: SIP_GTHE3_CHANNEL
Verilog Syntax Tree: item dag (VST_DAG_ITEM)
Decompile: unable to decompile type 910
Verilog Syntax Tree: parameter definition declaration (VST_D_DEFPARAM)
Scope: SIP_GTHE3_CHANNEL
Decompile: unable to decompile type 538
Verilog Syntax Tree: indexed vector type (VST_T_INDEXED_VEC)
Decompile: integer
Verilog Syntax Tree: sequential block statement (VST_S_SEQ_BLOCK)
Scope: SIP_GTHE3_CHANNEL
Verilog Syntax Tree: register declaration (VST_D_REG)
Scope: SIP_GTHE3_CHANNEL
Decompile: reg veam_drp_push
Verilog Syntax Tree: event or expression (VST_E_EVENT_OR)
Decompile: BUT.Ichannelfull.veam.gen_mc_tco_comlgcfg0 or veam_drp_push
Verilog Syntax Tree: nonblocking assignment statement (VST_S_NONBLOCKING_ASSIGNMENT)
Scope: SIP_GTHE3_CHANNEL
Decompile: BUT.Ichannelfull.veam.gen_mc_tco_comlgcfg0
Verilog Syntax Tree: event control expression (VST_E_EVENT_CONTROL)
Scope: SIP_GTHE3_CHANNEL
Decompile: @<>
Verilog Syntax Tree: concatenation expression (VST_E_CONCATENATION)
Decompile: {BUT.Idrpchdual.Idrp_top2.Idrp0.I4.I1.I3.Imc_vdd.mcell[15],BUT.Idrpchdual.Idrp_top2.Idrp0.I4.I1.I3.Imc_vdd.mcell[14],BUT.Idrpchdual.Idrp_top2.Idrp0.I4.I1.I3.Imc_vdd.mcell[13],BUT.Idrpchdual.Idrp_top2.Idrp0.I4.I1.I3.Imc_vdd.mcell[12],BUT.Idrpchdual.Idrp_to
Verilog Syntax Tree: hierarchical reference declaration (VST_D_OOMR)
Decompile: BUT.Idrpchdual.Idrp_top2.Idrp0.I4.I1.I3.Imc_vdd.mcell
Verilog Syntax Tree: bit select expression (VST_E_BIT_SELECT)
Decompile: BUT.Idrpchdual.Idrp_top2.Idrp0.I4.I1.I3.Imc_vdd.mcell[0]
Verilog Syntax Tree: logic type (VST_T_LOGIC)
Decompile: reg
Verilog Syntax Tree: number expression (VST_E_NUMBER)
Decompile: 0
Verilog Syntax Tree: hierarchical reference type (VST_T_OOMR)
Verilog Syntax Tree: name component oomr (VST_OOMR_NAME_COMPONENT)
Decompile: BUT.Ichannelfull.veam.gen_mc_tco_comlgcfg0
Intermediate File: root (IF_ROOT)
Intermediate File: string (IF_STRING)
Decompile: BUT.Idrpchdual.Idrp_top2.Idrp0.I4.I1.I3.Imc_vdd.mcell
csi-xmvlog - CSI: investigation complete took 0.018 secs, send this file to Cadence Support

Xcelium_Incubation_General 1.0 - Failed

Can anyone share XCELIUMMAIN_18.03.001 instalation packages..?

是license问题?