DC综合报错-Clock get used as data. (ELAB-305)

DC综合时，报错，但是这个get信号不是时钟信号，求大神指导怎么修改。NAME
ELAB-305 (error) %s Clock %s used as data.

DESCRIPTION
Youreceivethiserrormessage because Presto hdl Compiler does not
allow clock signals to be used for purposes other than clocking.

WHAT NEXT
Remove the unsupported code from your design.

verilog代码
module contral ( reset,
get,cancel,
money_all,//所需的总钱数
cin_all, //投入的总钱数
mout,//找零钱数
zflag,//找零结束标志
tflag,//出票结束标志
finish,//出钱信号
finishp //出票信号
);
input reset,zflag,tflag;
input get,cancel;
input[6:0] money_all;
input [6:0] cin_all;

output[6:0] mout;
output finish,finishp;

reg [6:0] mout;
reg finish,finishp;

//找零钱数计算部分
always @ (negedge resetor posedge cancel or posedge get or posedge zflag )//确认键和取消键应该是高脉冲，而不应该持续很长时间
begin
if(！reset)
begin
mout <= 7'd0;
end
else
if(cancel)
begin
mout <= cin_all;
end
else
if(zflag)
begin
mout <=7'd0 ;
end
else
if((get == 1)&&(cin_all < money_all))
begin
mout <= cin_all;//当钱数不够时是可以按确认时自动退出已投的钱，任意时刻均可以按取消即可退出所有已投的钱
end
else
if((get == 1)&&(cin_all >= money_all ))
begin
mout <= cin_all - money_all;//确认购票
end
else
begin
mout <=7'd0;
end
end
//找零结束，显示找零结束
always @ (negedge resetor posedge cancel or posedge get or posedge zflag )
begin
if(！reset)
begin
finish <= 1'b0;
end
else
if(cancel)
begin
finish <= 1'b1;
end
else
if(zflag)
begin
finish <= 1'b0;
end
else
if((get == 1)&&(cin_all < money_all))
begin
finish <= 1'b1;//当钱数不够时是可以按确认时自动退出已投的钱，任意时刻均可以按取消即可退出所有已投的钱
end
else
if((get == 1)&&(cin_all >= money_all ))
begin
finish <= 1'b1;
end
else
begin
finish <= 1'b0;
end
end

//投入的总钱数大于所需的钱数并且确认买票的时候显示找零信息
always @ (negedge resetor posedge cancel or posedge get or posedge tflag)
begin
if(！reset)
begin
finishp <= 1'b0;
end
else
if(cancel)
begin
finishp <= 1'b0;
end
else
if(tflag)
begin
finishp <= 1'b0;
end
else
if((get == 1)&&(cin_all >= money_all ))
begin
finishp <= 1'b1;
end
else
begin
finishp <= 1'b0;
end
end
endmodule