Minimize Sleep Mode Power Consumption due to Leakage in Sub-100nm in CMOS

A Novel Circuit Design Technique to Minimize Sleep Mode Power Consumption due to
Leakage Power in the Sub-100nm Wide Gates in CMOS Technology

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http://docs.google.com/viewer?a=v&q=cache:bVowKqokLyQJ:www.idosi.org/wasj/wasj4%285%29/ ... stor+design&hl=en&gl=in&sig=AHIEtbRQWVT21AP9N4210iAyqv7n-8EmIA

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http://www.idosi.org/wasj/wasj4(5)/2.pdf

多谢分享

thanks

THANK YOU