Cadence SoC Encounter 8.1 (Rapidshare)

With the Cadence® SoC Encounter™ RTL-to-GDSII System, engineers can account for the effects of interconnect across the entire chip—from the outset of the implementation cycle. It combines RTL synthesis, silicon virtual prototyping, automated floorplan synthesis, clock network synthesis, design for manufacturability and yield, low-power and mixed-signal design support, and nanometer routing. It also offers the latest capabilities to support advanced 65nm and 45nm designs.
Features/Benefits
* Supports multiple implementation styles with built-in power-planning, floorplanning, and signal integrity analysis
* Supports multiple methodologies for flip-chip implementation, promoting concurrent chip/package design
* Provides a statistical static timing analysis solution and standardized ECSM library models
* Incorporates cutting-edge yield and low-power design capabilities
* Handles 50M+ gate designs at 90nm and below


I reuploaded the correct image. Old files are removed.

Download:
http://rapidshare.com/files/325425951/Cadence_SoC_Encounter_8.1.7z.001
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Password:
mj

Thanks！

顶你！

有没有update

how can i combine these files?

Thanks a lot

Thanks！

好东西，一定要顶的！

7zip压缩的有问题，解压后文件名都错了！

需要用hjsplit合并文件
嘿嘿
谁把它下载完，然后传到纳米盘?