6735P上调试w1024 h600的屏显示不完整，有朋友遇到过吗
时间：10-02
整理：3721RD
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请问下mt6735V 1503-CPAHHAH BTTAY306是6735的，还是6735M的?
[USBD] USB PRB0 LineState: 0
[USBD] USB cable/ No Cable inserted！
[PLFM] Keep stay in USB Mode
[PWRAP] pwrap_init_preloader
[PWRAP] pwrap_init
[PWRAP] start reset wrapper
[PWRAP] the reset register =80
[PWRAP] PMIC_WRAP_STAUPD_GRPEN =0x0,it should be equal to 0xc
[PWRAP] _pwrap_init_reg_clock
[PWRAP] have cipher
[PWRAP] _pwrap_init_signature
[PWRAP] mt_pwrap_init PMIC_WRAP_STAUPD_GRPEN(3D)
[PWRAP] mt_pwrap_init-- use D1 or D3
[PWRAP] mt_pwrap_init---- debug15,FFFFFBFF
[PWRAP] after MT6328 pwrap_write
[PWRAP] write MT6328 Test pass
[PWRAP] Read 6328 Test pass,return_value=0
[PMIC_WRAP]wrap_init pass,the return value=0.
[pmic_init] Preloader Start..................
[pmic_init] MT6328 CHIP Code = 0x2820
bat is exist
[pmic_init] turn off usbdl wo Battery..................
just_rst = 0
[6328] is_efuse_trimed=0x1,[0xC5C]=0x8000
[6328] efuse_data[0x0]=0x0
[6328] efuse_data[0x1]=0xD144
[6328] efuse_data[0x2]=0xD144
[6328] efuse_data[0x3]=0xFBEF
[6328] efuse_data[0x4]=0xFBEF
[6328] efuse_data[0x5]=0x4400
[6328] efuse_data[0x6]=0x4400
[6328] efuse_data[0x7]=0x400
[6328] efuse_data[0x8]=0x400
[6328] efuse_data[0x9]=0x643C
[6328] efuse_data[0xA]=0x643C
[6328] efuse_data[0xB]=0x0
[6328] efuse_data[0xC]=0x0
[6328] efuse_data[0xD]=0x74
[6328] efuse_data[0xE]=0x0
[6328] efuse_data[0xF]=0x0
[6328] efuse_data[0x10]=0x0
[6328] efuse_data[0x11]=0x0
[6328] efuse_data[0x12]=0x0
[6328] efuse_data[0x13]=0x0
[6328] efuse_data[0x14]=0x0
[6328] efuse_data[0x15]=0x0
[6328] efuse_data[0x16]=0x0
[6328] efuse_data[0x17]=0x0
[6328] efuse_data[0x18]=0x0
[6328] efuse_data[0x19]=0x0
[6328] efuse_data[0x1A]=0x0
[6328] efuse_data[0x1B]=0x0
[6328] efuse_data[0x1C]=0x0
[6328] efuse_data[0x1D]=0x0
[6328] efuse_data[0x1E]=0x0
[6328] efuse_data[0x1F]=0x0
[upmu_set_rg_vio18_184] old cal=0 new cal=14.
[pmic_init] Reg[0x2A0]=0X301
[pmic_init] Done...................
[mmc_init]: msdc0 start mmc_init_host() in PL...
[msdc_init]: msdc0 Host controller intialization start
[MSDC]config VEMC to 3V in preloader
[SD0] Pins mode(1), none(0), down(1), up(2), keep(3)
[SD0] Pins mode(2), none(0), down(1), up(2), keep(3)
[MSDC]config VEMC to 3V in preloader
[info][msdc_set_startbit 1242] read data start bit at rising edge
[info][msdc_config_clksrc] input clock is 400000kHz
[SD0] Bus Width: 1
[info][msdc_config_clksrc] input clock is 400000kHz
[info][msdc_set_startbit 1242] read data start bit at rising edge
[SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) div(385) DS(0) RS(0)
[msdc_init]: msdc0 Host controller intialization done
[mmc_init]: msdc0 start mmc_init_card() in PL...
[mmc_init_card]: start
[info][msdc_config_clksrc] input clock is 400000kHz
[info][msdc_set_startbit 1242] read data start bit at rising edge
[SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) div(385) DS(0) RS(0)
[SD0] Bus Width: 8
[SD0] Switch to High-Speed mode！
[info][msdc_config_clksrc] input clock is 400000kHz
[info][msdc_set_startbit 1242] read data start bit at rising edge
[SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(2) DDR(1) div(192) DS(0) RS(0)
[SD0] Bus Width: 8
[SD0] Size: 7456 MB, Max.Speed: 52000 kHz, blklen(512), nblks(15269888), ro(0)
[mmc_init_mem_card 3144][SD0] Initialized, eMMC50
before host->cur_bus_clk(259740)
[info][msdc_config_clksrc] input clock is 400000kHz
[info][msdc_set_startbit 1242] read data start bit at rising edge
[SD0] SET_CLK(52000kHz): SCLK(50000kHz) MODE(2) DDR(1) div(1) DS(0) RS(0)
host->cur_bus_clk(50000000)
[mmc_init_card]: finish successfully
[EMI] mcp_dram_num:2,discrete_dram_num:0,enable_combo_dis:0
[EMI] index(0) emmc id match failed
found:1,i:1
[PLFM] Init I2C: OK(0)
[PLFM] Init PWRAP: OK(0)
[PLFM] Init PMIC: OK(0)
[PLFM] chip_code[321]
[PLFM] chip_ver[0]
[PTP] >> ptp_init()
[PTP] >> get_devinfo()
[PTP] << get_devinfo():322
[PTP] >> ptp_init_det()
[PTP] VCORE voltage bin to 1.05V
[PTP] << ptp_init_det():444
[PTP] PTP set volt: 0x00000048
[PTP] 0x00000057
[PTP] 0x00000056
[PTP] 0x00000055
[PTP] 0x00000054
[PTP] 0x00000053
[PTP] 0x00000052
[PTP] 0x00000051
[PTP] 0x00000050
[PTP] 0x0000004F
[PTP] 0x0000004E
[PTP] 0x0000004D
[PTP] 0x0000004C
[PTP] 0x0000004B
[PTP] 0x0000004A
[PTP] 0x00000049
[PTP] 0x00000048
[PTP] M_HW_RES0 = 0x10D13A34
[PTP] M_HW_RES1 = 0x006A0000
[PTP] M_HW_RES2 = 0x00000006
[PTP] M_HW_RES3 = 0x00364EE3
[PTP] M_HW_RES4 = 0x00000000
[PTP] M_HW_RES5 = 0x00000003
[PTP] << ptp_init():1032
[BLDR] Build Time: 20150323-203315
[DDR Reserve] ddr reserve mode not be enabled yet
RGU rgu_release_rg_dramc_conf_iso:mtk_WDT_DEBUG_CTL(590200F1)
RGU rgu_release_rg_dramc_iso:MTK_WDT_DEBUG_CTL(590200F1)
RGU rgu_release_rg_dramc_sref:MTK_WDT_DEBUG_CTL(590200F1)
DDR is in self-refresh. 200F1
DDR is in self-refresh. 200F1
DDR is in self-refresh. 200F1
==== Dump RGU Reg ========
RGU MODE: 4D
RGU LENGTH: FFE0
RGU STA: 0
RGU INTERVAL: FFF
RGU SWSYSRST: 8000
==== Dump RGU Reg End ====
RGU: g_rgu_satus:0
mtk_wdt_mode_config mode value=10, tmp:22000010
PL P ON
WDT does not trigger reboot
mtk_wdt_mode_config mode value=5D, tmp:2200005D
WDT NONRST=0X20000000
WDT IRQ_EN=0x340002
WDT REQ_EN=0x3C0002
RGU mtk_wdt_init:MTK_WDT_DEBUG_CTL(590200F3)
Enter mtk_kpd_GPIO_set！
after set KP enable: KP_SEL = 0x0 ！
[RTC] get_frequency_meter: input=0x0, ouput=5
[RTC] get_frequency_meter: input=0x0, ouput=3967
[RTC] get_frequency_meter: input=0x0, ouput=5
[RTC] get_frequency_meter: input=0x0, ouput=0
[RTC] get_frequency_meter: input=0x0, ouput=0
[RTC] bbpu = 0x1, con = 0x84A7, osc32con = 0x7B00, sec = 0x21BF, yea = 0x2
rtc_first_boot_init
[RTC] get_frequency_meter: input=0x0, ouput=5
[RTC] get_frequency_meter: input=0x0, ouput=3967
[RTC] get_frequency_meter: input=0x0, ouput=5
[RTC] get_frequency_meter: input=0x0, ouput=0
[RTC] get_frequency_meter: input=0x0, ouput=0
OSC32CON_ANALOG_SETTING = 0x7B00
rtc_2sec_stat_clear
rtc_2sec_reboot_check 0x21BF
rtc_2sec_stat_clear
[RTC] irqsta = 0x0, pdn1 = 0x0, pdn2 = 0x201, spar0 = 0xC0, spar1 = 0x800
[RTC] new_spare0 = 0x0, new_spare1 = 0x1, new_spare2 = 0x1, new_spare3 = 0x1
[RTC] bbpu = 0x1, con = 0x4A6, cali = 0x21BF
pl pmic powerkey Release
[pmic_IsUsbCableIn] 1
[PLFM] USB/charger boot！
[RTC] rtc_bbpu_power_on done
mt_get_dram_type() 0x3
[EMI] LPDDR3
[Check]mt_get_mdl_number 0x1
[EMI] eMMC/NAND ID = 15,1,0,51,37,32,53,4D,42,0,E5,D6,C6,2A,C1,85
[EMI] MDL number = 1
[EMI] emi_set eMMC/NAND ID = 15,1,0,51,37,32,53,4D,42,0,0,0,0,0,0,0
Start REXTDN SW calibration...
enable P drive (initial settings), 0x0644:27Dh
2.1. DRVP 0x00c0[15:12]:0h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:1000h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:2000h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:3000h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:4000h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:5000h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:6000h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:7000h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:8000h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:9000h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:A000h
2.2. CMPOP 0x03dc[31]:80000000h
P drive:10
enable N drive (initial settings), 0x0644:17Dh
4.1. DRVN 0x00c0[11:8]:A000h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:A100h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:A200h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:A300h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:A400h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:A500h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:A600h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:A700h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:A800h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:A900h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:AA00h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:AB00h
4.2.CMPON 0x3dc[30]:40000000h
N drive:10
drvp=10,drvn=10
=============================================
X-axis: DQS Gating Window Delay (Fine Scale)
Y-axis: DQS Gating Window Delay (Coarse Scale)
=============================================
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
--------------------------------------------------------------------------------
0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0010:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0011:| 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0012:| 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
0013:| 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0
0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rank 0 coarse tune value selection : -404,
rank 0 coarse = 18
rank 0 fine = 56
==============================================================
DATLAT calibration
==============================================================
DATLAT Default value = 0x8
TAP=0, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=1, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=2, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=3, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=4, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=5, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=6, err_value=0xFBFF7AFF, begin=0, first=255, sum=0
TAP=7, err_value=0x0, begin=1, first=7, sum=1
TAP=8, err_value=0x0, begin=1, first=7, sum=2
TAP=9, err_value=0x0, begin=1, first=7, sum=3
TAP=10, err_value=0x0, begin=1, first=7, sum=4
TAP=11, err_value=0x0, begin=1, first=7, sum=5
TAP=12, err_value=0x0, begin=1, first=7, sum=6
TAP=13, err_value=0x0, begin=1, first=7, sum=7
TAP=14, err_value=0x0, begin=1, first=7, sum=8
TAP=15, err_value=0x0, begin=1, first=7, sum=9
first_step=7 total pass=9 best_step=8
=============================================
X-axis: DQS Gating Window Delay (Fine Scale)
Y-axis: DQS Gating Window Delay (Coarse Scale)
=============================================
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
--------------------------------------------------------------------------------
0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0010:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
0011:| 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0012:| 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
0013:| 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0
0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rank 1 coarse tune value selection : -404,
rank 1 coarse = 18
rank 1 fine = 56
==============================================================
DATLAT calibration
==============================================================
DATLAT Default value = 0x8
TAP=0, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=1, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=2, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=3, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=4, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=5, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=6, err_value=0xB9FFFAF7, begin=0, first=255, sum=0
TAP=7, err_value=0x0, begin=1, first=7, sum=1
TAP=8, err_value=0x0, begin=1, first=7, sum=2
TAP=9, err_value=0x0, begin=1, first=7, sum=3
TAP=10, err_value=0x0, begin=1, first=7, sum=4
TAP=11, err_value=0x0, begin=1, first=7, sum=5
TAP=12, err_value=0x0, begin=1, first=7, sum=6
TAP=13, err_value=0x0, begin=1, first=7, sum=7
TAP=14, err_value=0x0, begin=1, first=7, sum=8
TAP=15, err_value=0x0, begin=1, first=7, sum=9
first_step=7 total pass=9 best_step=8
DQS loop = 15, cmp_err_1 = 0
DQS loop = 14, cmp_err_1 = 0
DQS loop = 13, cmp_err_1 = 0
DQS loop = 12, cmp_err_1 = 0
DQS loop = 11, cmp_err_1 = 0
DQS loop = 10, cmp_err_1 = 0
DQS loop = 9, cmp_err_1 = 0
DQS loop = 8, cmp_err_1 = 0
DQS loop = 7, cmp_err_1 = 0
DQS loop = 6, cmp_err_1 = 0
DQS loop = 5, cmp_err_1 = 0
DQS loop = 4, cmp_err_1 = 0
DQS loop = 3, cmp_err_1 = 0
DQS loop = 2, cmp_err_1 = 0
DQS loop = 1, cmp_err_1 = 0
DQS loop = 0, cmp_err_1 = 0
DQ loop=15, cmp_err_1 = F020A00
DQ loop=14, cmp_err_1 = A000A00
DQ loop=13, cmp_err_1 = 2000800
DQ loop=12, cmp_err_1 = 800
DQ loop=11, cmp_err_1 = 0
DQ loop=10, cmp_err_1 = 0
DQ loop=9, cmp_err_1 = 0
DQ loop=8, cmp_err_1 = 0
DQ loop=7, cmp_err_1 = 0
DQ loop=6, cmp_err_1 = 0
DQ loop=5, cmp_err_1 = 0
DQ loop=4, cmp_err_1 = 0
DQ loop=3, cmp_err_1 = 0
DQ loop=2, cmp_err_1 = 0
DQ loop=1, cmp_err_1 = 0
DQ loop=0, cmp_err_1 = 0
byte:0, (DQS,DQ)=(0,0)
byte:1, (DQS,DQ)=(2,0)
byte:2, (DQS,DQ)=(0,0)
byte:3, (DQS,DQ)=(1,0)
[EMI] DRAMC calibration passed
[DRAM] DFS rank0 coarse fine : 18 56, rank1 coarse fine :18 56
DFS could be enable
[MEM] complex R/W mem test pass
RGU rgu_dram_reserved:MTK_WDT_MODE(220000DD)
[Dram_Buffer] dram_buf_t size: 0x1998C0
[Dram_Buffer] part_hdr_t size: 0x200
[Dram_Buffer] sizeof(boot_arg_t): 0x168
[Dram_Buffer] g_dram_buf start addr: 0x42000000
[Dram_Buffer] g_dram_buf->msdc_gpd_pool start addr: 0x42199800
[Dram_Buffer] g_dram_buf->msdc_bd_pool start addr: 0x4���ӗ��}��[�A
� ���u�#NTLuFd sram(0x4B1D8D57) sig mismatch���g�X'H
RAM_CONSOLE start: 0x43F00000, size: 0x10000, sig: 0x40040000
RAM_CONSOLE wdt status (0x43F00040)=0x0
[PLFM] Init Boot Device: OK(0)
Enter mtk_kpd_gpio_set！
mtk detect key function pmic_detect_homekey MTK_PMIC_RST_KEY = 17
pl pmic FCHRKEY Release
0:dram_rank_size:20000000
1:dram_rank_size:20000000
0:dram_rank_size:20000000
1:dram_rank_size:20000000
orig_dram_info[0] start: 0x0000000040000000, size: 0x0000000020000000
orig_dram_info[1] start: 0x0000000060000000, size: 0x0000000020000000
CUSTOM_CONFIG_MAX_DRAM_SIZE: 0x0000000100000000
total_dram_size: 0x0000000040000000, max_dram_size: 0x0000000100000000
�����������[GPT_PL]Parsing Primary GPT now...
[GPT_PL][0]name=proinfo, part_id=8, start_sect=0x400, nr_sects=0x1800
[GPT_PL][1]name=nvram, part_id=8, start_sect=0x1C00, nr_sects=0x2800
[GPT_PL][2]name=protect1, part_id=8, start_sect=0x4400, nr_sects=0x5000
[GPT_PL][3]name=protect2, part_id=8, start_sect=0x9400, nr_sects=0x5000
[GPT_PL][4]name=lk, part_id=8, start_sect=0xE400, nr_sects=0x400
[GPT_PL][5]name=para, part_id=8, start_sect=0xE800, nr_sects=0x400
[GPT_PL][6]name=boot, part_id=8, start_sect=0xEC00, nr_sects=0x8000
[GPT_PL][7]name=recovery, part_id=8, start_sect=0x16C00, nr_sects=0x8000
[GPT_PL][8]name=logo, part_id=8, start_sect=0x1EC00, nr_sects=0x4000
[GPT_PL][9]name=expdb, part_id=8, start_sect=0x22C00, nr_sects=0x5000
[GPT_PL][10]name=seccfg, part_id=8, start_sect=0x27C00, nr_sects=0x400
[GPT_PL][11]name=oemkeystore, part_id=8, start_sect=0x28000, nr_sects=0x1000
[GPT_PL][12]name=secro, part_id=8, start_sect=0x29000, nr_sects=0x3000
[GPT_PL][13]name=keystore, part_id=8, start_sect=0x2C000, nr_sects=0x4000
[GPT_PL][14]name=tee1, part_id=8, start_sect=0x30000, nr_sects=0x2800
[GPT_PL][15]name=tee2, part_id=8, start_sect=0x32800, nr_sects=0x2800
[GPT_PL][16]name=frp, part_id=8, start_sect=0x35000, nr_sects=0x800
[GPT_PL][17]name=nvdata, part_id=8, start_sect=0x35800, nr_sects=0x10000
[GPT_PL][18]name=metadata, part_id=8, start_sect=0x45800, nr_sects=0x12800
[GPT_PL][19]name=system, part_id=8, start_sect=0x58000, nr_sects=0x300000
[GPT_PL][20]name=cache, part_id=8, start_sect=0x358000, nr_sects=0xC8000
[GPT_PL][21]name=userdata, part_id=8, start_sect=0x420000, nr_sects=0xA67C00
[GPT_PL][22]name=flashinfo, part_id=8, start_sect=0xE87C00, nr_sects=0x8000
[GPT_PL]Success to find valid GPT.
[PART] blksz: 512B
[PART] [0x0000000000080000-0x000000000037FFFF] "proinfo" (6144 blocks)
[PART] [0x0000000000380000-0x000000000087FFFF] "nvram" (10240 blocks)
[PART] [0x0000000000880000-0x000000000127FFFF] "protect1" (20480 blocks)
[PART] [0x0000000001280000-0x0000000001C7FFFF] "protect2" (20480 blocks)
[PART] [0x0000000001C80000-0x0000000001CFFFFF] "lk" (1024 blocks)
[PART] [0x0000000001D00000-0x0000000001D7FFFF] "para" (1024 blocks)
[PART] [0x0000000001D80000-0x0000000002D7FFFF] "boot" (32768 blocks)
[PART] [0x0000000002D80000-0x0000000003D7FFFF] "recovery" (32768 blocks)
[PART] [0x0000000003D80000-0x000000000457FFFF] "logo" (16384 blocks)
[PART] [0x0000000004580000-0x0000000004F7FFFF] "expdb" (20480 blocks)
[PART] [0x0000000004F80000-0x0000000004FFFFFF] "seccfg" (1024 blocks)
[PART] [0x0000000005000000-0x00000000051FFFFF] "oemkeystore" (4096 blocks)
[PART] [0x0000000005200000-0x00000000057FFFFF] "secro" (12288 blocks)
[PART] [0x0000000005800000-0x0000000005FFFFFF] "keystore" (16384 blocks)
[PART] [0x0000000006000000-0x00000000064FFFFF] "tee1" (10240 blocks)
[PART] [0x0000000006500000-0x00000000069FFFFF] "tee2" (10240 blocks)
[PART] [0x0000000006A00000-0x0000000006AFFFFF] "frp" (2048 blocks)
[PART] [0x0000000006B00000-0x0000000008AFFFFF] "nvdata" (65536 blocks)
[PART] [0x0000000008B00000-0x000000000AFFFFFF] "metadata" (75776 blocks)
[PART] [0x000000000B000000-0x000000006AFFFFFF] "system" (3145728 blocks)
[PART] [0x000000006B000000-0x0000000083FFFFFF] "cache" (819200 blocks)
[PART] [0x0000000084000000-0x00000001D0F7FFFF] "userdata" (10910720 blocks)
[PART] [0x00000001D0F80000-0x00000001D1F7FFFF] "flashinfo" (32768 blocks)
[ROM_INFO] 'v2','0x0','0x0','0x0','0x2C00'
[SEC_K] SML KEY AC = 0
[SEC_K] SBC_PUBK Found
[SEC] AES Legacy : 0
[SEC] SECCFG AC : 1
[LIB] Loading SEC config
[LIB] Name =
[LIB] Config = 0x22, 0x22
[LIB] SECRO (ac, ac_offset, ac_length) = (0x1, 0x40, 0x40)
0x31,0x41,0x35,0x35
[SEC] DBGPORT (0 1)
[SEC] read '0x4F80000'
0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,
[LIB] CFG read size '0x2000' '0x1860'
0x0
[LIB] HW DEC
0x170A9D79
[LIB] SEC CFG doesn't exist
[SEC] init fail '0x3000'
[LIB] seccfg magic is incorrect
[PLFM] USB cable in
[TOOL] USB enum timeout (Yes), handshake timeout(Yes)
[USBD] USB Full Speed
[TOOL] Enumeration(Start)
[USBD] USB High Speed
[USBD] USB High Speed
[TOOL] Enumeration(End): OK 401ms
usbdl_flush timeout
usbdl_flush timeout
[TOOL] : usb listen timeout
[TOOL] <USB> cannot detect tools！
[TOOL] <UART> listen ended, receive size:0！
[TOOL] <UART> wait sync time 150ms->5ms
[TOOL] <UART> receieved data: ()
[LIB] NS-CHIP
[SBC] Don't check
Device APC domain init setup:
Domain Setup (0x0)
Domain Setup (0x0)
Domain Setup (0x0)
Device APC domain after setup:
Domain Setup (0x0)
Domain Setup (0x1020000)
warning: size is not 2MB aligned
mblock[0].start: 0x0000000040000000, sz: 0x0000000020000000, limit: 0x0000000100000000, max_addr: 0x0000000000000000, max_rank: 1, target: -1, mblock[0
mblock_reserve dbg[0]: 1, 1, 1, 1
mblock[1].start: 0x0000000060000000, sz: 0x0000000020000000, limit: 0x0000000100000000, max_addr: 0x0000000060000000, max_rank: 1, target: 0, mblock[]1
mblock_reserve dbg[1]: 1, 1, 1, 1
mblock_reserve: 000000007FFC0000 - 0000000080000000 from mblock 1
[PART] Image with part header
[PART] name : LK
[PART] addr : FFFFFFFFh mode : -1
[PART] size : 308556
[PART] magic: 58881688h
[PART] load "lk" from 0x0000000001C80200 (dev) to 0x41E00000 (mem) [SUCCESS]
[PART] load speed: 50220KB/s, 308556 bytes, 6ms
[PART] Image with part header
[PART] name : ATF
[PART] addr : FFFFFFFFh mode : 0
[PART] size : 53248
[PART] magic: 58881688h
[PART] load "tee1" from 0x0000000006000200 (dev) to 0x43000DC0 (mem) [SUCCESS]
[PART] load speed: 13000KB/s, 53248 bytes, 4ms
[TZ_INIT] tee_verify_image : passed
[BLDR] bldr load tee part ret=0x0, addr=0x43001000
[BLDR] part_load_raw_part ret=0x0
[BLDR] part_load_images ret=0x0
bat is exist
[pmic_init] turn off usbdl wo battery..................
[PLFM],64S3,boot_opt=0x0
[PLFM],32N2,boot_opt=0x6
[PLFM],64N2,boot_opt=0x4
[PLFM] boot to LK by ATAG.
boot reason: 1
boot mode: 0
META COM0: 0
rank[0] size: 0x20000000
rank[1] size: 0x1FFC0000
tee reserved mem: 0x000000007FFC0000, 0x0000000000040000
md_type[0]: 0x0
md_type[1]: 0x0
boot time: 4664
DDR reserve mode: enable = 0, success = 0
dram buffer size: 1677504
[PTP][preloader]first_volt = 0x68
[PTP][preloader]second_volt = 0x48
[PTP][preloader]third_volt = 0x48
[PTP][preloader]have_550 = 0x0
SMC: 0x0
LK: 0x6
KERNEL: 0x4
NONSEC SRAM Addr: 0x10DC00
NONSEC SRAM Size: 0x2400
[TZ_INIT] hwuid[0] : 0x1B4DFAF8
[TZ_INIT] hwuid[1] : 0xCCE7DB22
[TZ_INIT] hwuid[2] : 0x434CB0D0
[TZ_INIT] hwuid[3] : 0x20922011
[TZ_INIT] HRID[0] : 0xE6FE37C6
[TZ_INIT] HRID[1] : 0xD7C9C7CB
[TZ_INIT] atf_log_port : 0x11002000
[TZ_INIT] atf_log_baudrate : 0xE1000
[TZ_INIT] atf_irq_num : 281
[TZ_INIT] ATF log buffer start : 0x7FFC0000
[TZ_INIT] ATF log buffer size : 0x40000
[TZ_INIT] ATF aee buffer start : 0x7FFFC000
[TZ_INIT] ATF aee buffer size : 0x4000
[BLDR] Others, jump to ATF
[BLDR] jump to 0x41E00000
[BLDR] <0x41E00000>=0xEA000007
[BLDR] <0x41E00004>=0xEA005B99
[TZ_SEC_CFG] SRAMROM Secure Addr 0xDC00
[TZ_SEC_CFG] SRAMROM Secure Control 0x0
[TZ_SEC_CFG] SRAMROM Secure Control 0xB69
[TZ_SEC_CFG] SRAMROM Secure Control 0x1B680B69
[TZ_INIT] ATF entry addr, aligned addr : 0x43001000, 0x43000000
[TZ_EMI_MPU] MPU [0x43000000-0x4302FFFF]
[TZ_INIT] set secure memory protection : 0x43000000, 0x4302FFFF (1)
[TZ_INIT] Jump to ATF, then 0x41E00000
[ATF][ 0.000000]BL33 boot argument location=0x42199880
[ATF][ 0.000000]BL33 boot argument size=0x168
[ATF][ 0.000000]BL33 start addr=0x41e00000
[ATF][ 0.000000]teearg addr=0x101000
[ATF][ 0.000000]atf_magic=0x4d415446
[ATF][ 0.000000]tee_support=0x0
[ATF][ 0.000000]tee_entry=0x0
[ATF][ 0.000000]tee_boot_arg_addr=0x101100
[ATF][ 0.000000]atf_log_port=0x11002000
[ATF][ 0.000000]atf_log_baudrate=0xe1000
[ATF][ 0.000000]atf_log_buf_start=0x7ffc0000
[ATF][ 0.000000]atf_log_buf_size=0x40000
[ATF][ 0.000000]atf_aee_debug_buf_start=0x7fffc000
[ATF][ 0.000000]atf_aee_debug_buf_size=0x4000
[ATF][ 0.000000]atf_irq_num=281
[ATF][ 0.000000]BL33_START_ADDRESS=0x41e00000
[ATF][ 0.000000]###@@@ MP0_MISC_CONFIG3:0x00000000 @@@###
[ATF][ 0.000000]###@@@ MP0_MISC_CONFIG3:0x0000e000 @@@###
[ATF][ 0.000000]mmap atf buffer : 0x7ffc0000, 0x40000
[ATF][ 0.000000]mmap atf buffer (force 2MB aligned): 0x7fe00000, 0x200000
NOTICE: BL3-1: v1.0(debug):e7d64d4
NOTICE: BL3-1: Built : 10:50:39, Mar 21 2015
[ATF][ 0.000000]sta=0x0 int=0xffc
[ATF][ 0.000000]is_power_on_boot: true
[ATF][ 0.000000]mt_log_setup - atf_buf_addr : 0x7ffc0100
[ATF][ 0.000000]mt_log_setup - atf_buf_size : 0x2bf00
[ATF][ 0.000000]mt_log_setup - atf_write_pos : 0x7ffc0100
[ATF][ 0.000000]mt_log_setup - atf_read_pos : 0x7ffc0100
[ATF][ 0.000000]mt_log_setup - atf_buf_lock : 0x0
[ATF][ 0.000000]mt_log_setup - mt_log_buf_end : 0x7ffebfff
[ATF][ 0.000000]mt_log_setup - ATF_CRASH_LAST_LOG_SIZE : 0x8000
[ATF][ 0.000000]mt_log_setup - ATF_EXCEPT_BUF_SIZE_PER_CPU : 0x1000
[ATF][ 0.000000]mt_log_setup - ATF_EXCEPT_BUF_SIZE : 0x8000
[ATF][ 0.000000]mt_log_setup - PLATFORM_CORE_COUNT : 0x8
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[0]: 0x7fff4000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[1]: 0x7fff5000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[2]: 0x7fff6000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[3]: 0x7fff7000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[4]: 0x7fff8000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[5]: 0x7fff9000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[6]: 0x7fffa000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[7]: 0x7fffb000
[ATF][ 0.000000]mt_log_setup - atf_crash_flag : 0x0
[ATF][ 0.000000]mt_log_setup - atf_crash_log_addr : 0x0
[ATF][ 0.000000]mt_log_setup - atf_crash_log_size : 0x0
[ATF][ 0.000000]ATF log service is registered (0x7ffc0000, aee:0x7fffc000)
[ATF][ 0.000000]BL3-1: v1.0(debug):e7d64d4
[ATF][ 0.000000]BL3-1: Built : 10:50:39, Mar 21 2015
INFO: BL3-1: Initializing runtime services
[ATF][ 0.000000][BL31] Jump to FIQD for initialization！
INFO: BL3-1: Preparing for EL3 exit to normal world, LK
INFO: BL3-1: Next image address = 0x41e00000
INFO: BL3-1: Next image spsr = 0x1d3
[ATF][ 0.000000][BL31] Final dump！
[0] kernel_boot_opt=4
[0] 64Bit Kernel
[0] WDT NONRST=0x20000000
[0] [LEDS]LK: leds_init: mt65xx_backlight_off
[0] [LEDS]LK: mt65xx_backlight_off
[0] [LEDS]LK: LCD-backlight level is 0
[0] [pmic_init] LK Start..................
[0] [pmic_init] MT6325 CHIP Code = 0x2820
[0] [pmic_init] Done
[10] platform_init()
[20] [mmc_init]: msdc0 start mmc_init_host() in LK...
[20] [msdc_init]: msdc0 Host controller intialization start
[20] [MSDC] config VEMC to 3V in lk
[20] [SD0] Pins mode(1), none(0), down(1), up(2), keep(3)
[20] [SD0] Pins mode(2), none(0), down(1), up(2), keep(3)
[20] [MSDC] config VEMC to 3V in lk
[20] [info][msdc_set_startbit 1247] read data start bit at rising edge
[20] [info][msdc_config_clksrc] input clock is 400000kHz
[20] [SD0] Bus Width: 1
[20] [info][msdc_config_clksrc] input clock is 400000kHz
[20] [info][msdc_set_startbit 1247] read data start bit at rising edge
[20] [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) div(385) DS(0) RS(0)
[20] [msdc_init]: msdc0 Host controller intialization done
[20] [mmc_init]: msdc0 start mmc_init_card()in LK...
[20] [mmc_init_card]: start
[140] [info][msdc_config_clksrc] input clock is 400000kHz
[140] [info][msdc_set_startbit 1247] read data start bit at rising edge
[140] [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) div(385) DS(0) RS(0)
[140] [SD0] Bus Width: 8
[160] [SD0] Switch to High-Speed mode！
[160] [info][msdc_config_clksrc] input clock is 400000kHz
[160] [info][msdc_set_startbit 1247] read data start bit at rising edge
[160] [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(2) DDR(1) div(192) DS(0) RS(0)
[160] [SD0] Bus Width: 8
[160] [SD0] Size: 7456 MB, Max.Speed: 52000 kHz, blklen(512), nblks(15269888), ro(0)
[160] [mmc_init_mem_card 3240][SD0] Initialized, eMMC50
[160] before host->cur_bus_clk(259740)
[180] [info][msdc_config_clksrc] input clock is 400000kHz
[180] [info][msdc_set_startbit 1247] read data start bit at rising edge
[180] [SD0] SET_CLK(52000kHz): SCLK(50000kHz) MODE(2) DDR(1) div(1) DS(0) RS(0)
[180] host->cur_bus_clk(50000000)
[180] [mmc_init_card]: finish successfully
[180] [mt_part_register_device]
[180] [GPT_LK]Parsing Primary GPT now...
[180] [GPT_LK][0]name=proinfo, part_id=8, start_sect=0x400, nr_sects=0x1800
[180] [GPT_LK][1]name=nvram, part_id=8, start_sect=0x1c00, nr_sects=0x2800
[180] [GPT_LK][2]name=protect1, part_id=8, start_sect=0x4400, nr_sects=0x5000
[180] [GPT_LK][3]name=protect2, part_id=8, start_sect=0x9400, nr_sects=0x5000
[180] [GPT_LK][4]name=lk, part_id=8, start_sect=0xe400, nr_sects=0x400
[190] [GPT_LK][5]name=para, part_id=8, start_sect=0xe800, nr_sects=0x400
[200] [GPT_LK][6]name=boot, part_id=8, start_sect=0xec00, nr_sects=0x8000
[200] [GPT_LK][7]name=recovery, part_id=8, start_sect=0x16c00, nr_sects=0x8000
[200] [GPT_LK][8]name=logo, part_id=8, start_sect=0x1ec00, nr_sects=0x4000
[200] [GPT_LK][9]name=expdb, part_id=8, start_sect=0x22c00, nr_sects=0x5000
[200] [GPT_LK][10]name=seccfg, part_id=8, start_sect=0x27c00, nr_sects=0x400
[200] [GPT_LK][11]name=oemkeystore, part_id=8, start_sect=0x28000, nr_sects=0x1000
[200] [GPT_LK][12]name=secro, part_id=8, start_sect=0x29000, nr_sects=0x3000
[200] [GPT_LK][13]name=keystore, part_id=8, start_sect=0x2c000, nr_sects=0x4000
[200] [GPT_LK][14]name=tee1, part_id=8, start_sect=0x30000, nr_sects=0x2800
[200] [GPT_LK][15]name=tee2, part_id=8, start_sect=0x32800, nr_sects=0x2800
[200] [GPT_LK][16]name=frp, part_id=8, start_sect=0x35000, nr_sects=0x800
[210] [GPT_LK][17]name=nvdata, part_id=8, start_sect=0x35800, nr_sects=0x10000
[220] [GPT_LK][18]name=metadata, part_id=8, start_sect=0x45800, nr_sects=0x12800
[220] [GPT_LK][19]name=system, part_id=8, start_sect=0x58000, nr_sects=0x300000
[220] [GPT_LK][20]name=cache, part_id=8, start_sect=0x358000, nr_sects=0xc8000
[220] [GPT_LK][21]name=userdata, part_id=8, start_sect=0x420000, nr_sects=0xa67c00
[220] [GPT_LK][22]name=flashinfo, part_id=8, start_sect=0xe87c00, nr_sects=0x8000
[220] [GPT_LK]Success to find valid GPT.
[220] [SD0] boot device found
[220] [upmu_is_chr_det] 1
[220] [PART_LK][get_part] para
[LK_ENV]ENV initialize sucess
[LK_ENV]env:
off-mode-charge=1
data_free_size_th=52428800
[220] [DISP]func|disp_LCM_probe
[220] [DISP]func|_display_interface_path_init
[240] [DISPCHECK]dpmgr create path SUCCESS(0x41e4df38)
[240] [DISPCHECK]dpmgr set dst module FINISHED(dsi0 )
[240] [DISP]func|ddp_dsi_init
[240] [DISPCHECK]dsi0 init finished
[240] [DISP]func|ddp_dsi_config
[240] [DISPCHECK][DDPDSI] DSI Mode: SYNC_EVENT_VDO_MODE
[240] [DISPCHECK][DDPDSI] LANE_NUM: 4,data_format: 0,vertical_sync_active: 0
[240] [DISPCHECK][DDPDSI] vact: 10, vbp: 23, vfp: 12, vact_line: 600, hact: 10, hbp: 160, hfp: 160, hblank: 0, hblank: 1105566796
[240] [DISPCHECK][DDPDSI] pll_select: 0, pll_div1: 0, pll_div2: 0, fbk_div: 0,fbk_sel: 0, rg_bir: 0
[240] [DISPCHECK][DDPDSI] rg_bic: 0, rg_bp: 0, PLL_CLOCK: 175, dsi_clock: 0, ssc_range: 0, ssc_disable: 0, compatibility_for_nvk: 0, cont_clock: 0
[240] [DISPCHECK][DDPDSI] lcm_ext_te_enable: 0, noncont_clock: 0, noncont_clock_period: 0
[240] [DISP]func|DSI_PHY_clk_setting
[240] [DISP][mipitx/inreg]0x10206190=0x00000000
[260] [DISP][mipitx/reg]0x14017004=0x00000020
[260] [DISP][mipitx/reg]0x14017014=0x00000000
[260] [DISP][mipitx/reg]0x14017010=0x00000000
[260] [DISP][mipitx/reg]0x1401700c=0x00000000
[260] [DISP][mipitx/reg]0x14017008=0x00000000
[260] [DISP]PLL config: LNT=0x0,clk=0x20,lan3=0x20,lan2=0x0,lan1=0x0,lan0=0x0
[260] [DISP][mipitx/reg]0x14017044=0x88492481
[260] [DISP][mipitx/reg]0x14017044=0x88492483
[260] [DISP][mipitx/reg]0x14017040=0x00000082
[260] [DISP][mipitx/reg]0x14017000=0x00000402
[260] [DISP][mipitx/reg]0x14017000=0x00000403
[260] [DISP][mipitx/reg]0x14017068=0x00000003
[260] [DISP][mipitx/reg]0x14017068=0x00000101
[260] [DISP][mipitx/reg]0x14017050=0x00000008
[260] [DISP][mipitx/reg]0x14017050=0x00000008
[260] [DISP][mipitx/reg]0x14017050=0x00000008
[260] [DISP][mipitx/reg]0x14017054=0x00000003
[260] [DISP][mipitx/reg]0x14017058=0x35000000
[260] [DISP][mipitx/reg]0x14017058=0x35d80000
[280] [DISP][mipitx/reg]0x14017058=0x35d89d00
[280] [DISP][mipitx/reg]0x14017058=0x35d89d89
[280] [DISP][mipitx/reg]0x14017054=0x00000003
[280] [DISP][mipitx/reg]0x14017054=0x01b10003
[280] [DISP][mipitx/reg]0x1401705c=0x065d0000
[280] [DISP][mipitx/reg]0x1401705c=0x065d065d
[280] [DISP][dsi_drv.c] PLL config:data_rate=350,txdiv=2,pcw=903388553,delta1=5,pdelta1=0x65d
[280] [DISP][mipitx/reg]0x14017054=0x01b10007
[280] [DISP][mipitx/reg]0x14017004=0x00000021
[280] [DISP][mipitx/reg]0x14017008=0x00000001
[280] [DISP][mipitx/reg]0x1401700c=0x00000001
[280] [DISP][mipitx/reg]0x14017010=0x00000001
[280] [DISP][mipitx/reg]0x14017014=0x00000001
[280] [DISP][mipitx/reg]0x14017050=0x00000009
[280] [DISP][mipitx/reg]0x14017060=0x00000000
[280] [DISP][mipitx/reg]0x14017060=0x00000001
[280] [DISP][mipitx/reg]0x14017040=0x00000082
[280] DISP/[DISP] - kernel - DSI_PHY_TIMCONFIG, Cycle Time = 23(ns), Unit Interval = 3(ns). , lane# = 4
[300] DISP/[DISP] - kernel - DSI_PHY_TIMCONFIG, HS_TRAIL = 4, HS_ZERO = 7, HS_PRPR = 3, LPX = 3, TA_GET = 15, TA_SURE = 4, TA_GO = 12, CLK_TRAIL = 5,
[300] [DISP]func|_display_interface_path_deinit
[300] [DISPCHECK]dsi0 init finished
[300] [DISP][mipitx/reg]0x14017084=0x00000001
[300] [DISP][mipitx/reg]0x14017084=0x00000003
[300] [DISP][mipitx/reg]0x14017084=0x00000013
[300] [DISP][mipitx/reg]0x14017084=0x00000033
[300] [DISP][mipitx/reg]0x14017084=0x00000033
[300] [DISP][mipitx/reg]0x14017084=0x00000033
[300] [DISP][mipitx/reg]0x14017084=0x00000133
[300] [DISP][mipitx/reg]0x14017084=0x00000333
[300] [DISP][mipitx/reg]0x14017084=0x00010333
[300] [DISP][mipitx/reg]0x14017084=0x00020333
[300] [DISP][mipitx/reg]0x14017084=0x00100333
[300] [DISP][mipitx/reg]0x14017084=0x00200333
[300] [DISP][mipitx/reg]0x14017080=0x00000001
[320] [DISP][mipitx/reg]0x14017050=0x00000008
[320] [DISP][mipitx/reg]0x14017064=0x00000020
[320] [DISP][mipitx/reg]0x14017040=0x00000882
[320] [DISP][mipitx/reg]0x14017004=0x00000020
[320] [DISP][mipitx/reg]0x14017008=0x00000000
[320] [DISP][mipitx/reg]0x1401700c=0x00000000
[320] [DISP][mipitx/reg]0x14017010=0x00000000
[320] [DISP][mipitx/reg]0x14017014=0x00000000
[320] [DISP][mipitx/reg]0x14017068=0x00000103
[320] [DISP][mipitx/reg]0x14017068=0x00000102
[320] [DISP][mipitx/reg]0x14017040=0x00000880
[320] [DISP][mipitx/reg]0x14017000=0x00000401
[320] [DISP][mipitx/reg]0x14017000=0x00000400
[320] [DISP][mipitx/reg]0x14017044=0x88492481
[320] [DISP][mipitx/reg]0x14017044=0x88492480
[320] [DISP][mipitx/reg]0x14017050=0x00000008
[320] [DISP][mipitx/reg]0x14017050=0x00000000
[320] [DISP][mipitx/reg]0x14017050=0x00000000
[340] [DISP][mipitx/reg]0x14017050=0x00000000
[340] [DISP][mipitx/reg]0x14017054=0x00000000
[340] [DISP][mipitx/reg]0x14017058=0x50000000
[340] [DISP][mipitx/reg]0x14017080=0x00000000
[340] [DISPCHECK]******** dump lcm driver information ********
[340] [DISPCHECK][LCM], name: n711_ek79007_wsvga_dsi_vdo
[340] [DISPCHECK][LCM] resolution: 1024 x 600
[340] [DISPCHECK][LCM] physical size: 0 x 0
[340] [DISPCHECK][LCM] physical size: 0 x 0
[340] [DISPCHECK][LCM] lcm_if:0, cmd_if:0
[340] [DISPCHECK][LCM] interface: unknown
[340] [DISPCHECK][LCM] Type: DSI
[340] [DISPCHECK][LCM] DSI Mode: SYNC_EVENT_VDO_MODE
[340] [DISPCHECK][LCM] LANE_NUM: 4,data_format: 0,vertical_sync_active: 0
[340] [DISPCHECK][LCM] vact: 10, vbp: 23, vfp: 12, vact_line: 600, hact: 10, hbp: 160, hfp: 160, hblank: 0, hblank: 1105506872
[350] [DISPCHECK][LCM] pll_select: 0, pll_div1: 0, pll_div2: 0, fbk_div: 0,fbk_sel: 0, rg_bir: 0
[360] [DISPCHECK][LCM] rg_bic: 0, rg_bp: 0, PLL_CLOCK: 175, dsi_clock: 0, ssc_range: 0, ssc_disable: 0, compatibility_for_nvk: 0, cont_clock: 0
[360] [DISPCHECK][LCM] lcm_ext_te_enable: 0, noncont_clock: 0, noncont_clock_period: 0
[360] [DISP]lcm handle is null, after probe:0x41e4e494
[360] [DISP]^^ DISP_GetVRamSize: 8716288 bytes
[360] warning: size is not 2MB aligned
[360] mblock[0].start: 0x40000000, sz: 0x20000000, limit: 0x100000000, max_addr: 0x0, max_rank: 1, target: -1, mblock[].rank: 0
[360] mblock_reserve dbg[0]: 1, 1, 1, 1
[360] mblock[1].start: 0x60000000, sz: 0x1ffc0000, limit: 0x100000000, max_addr: 0x60000000, max_rank: 1, target: 0, mblock[].rank: 1
[360] mblock_reserve dbg[1]: 1, 1, 1, 1
[360] mblock_reserve: 7f770000 - 7ffc0000 from mblock 1
[360] FB base = 0x7f770000, FB size = 8716288
[370] fb_va: 0x7f770000, fb_pa: 0x7f770000, fb_pa_k: 0x7f770000
[380] [DISP]func|primary_display_init
[LK_ENV]get_env DFO
[380] [DISP]env buffer = <null>
[380] [DISP]env buffer = NULL
[380] [DISP]LCM_FAKE_WIDTH = [DEC]0 [HEX]0x00000000
[380] [DISP]LCM_FAKE_HEIGHT = [DEC]0 [HEX]0x00000000
[380] [DISP]LCM Resolution will be changed, original: 1024x600, now: 0x0
[380] [DISP]ERROR:Invalid resolution: 0x0
[380] [DISP]ERROR:[DISP_DFO]WARNING！ Change LCM Resolution FAILED！
[380] [DISPCHECK]disp_lcm_probe SUCCESS
[380] [DISP]func|disp_lcm_get_params
[380] [DISP]func|_build_path_direct_link
[380] [DISPCHECK]dpmgr create path SUCCESS(0x41e4df38)
[380] [DISPCHECK]dpmgr set dst module FINISHED(dsi0 )
[380] [DISPCHECK]primary display is DIRECT LINK MODE
[380] [DISPCHECK]primary display BUILD cmdq trigger loop finished
[380] [DISPCHECK]primary display START cmdq trigger loop finished
[380] [DISP]func|disp_lcm_is_video_mode
[400] [DISP]func|ddp_dsi_init
[400] [DISPCHECK]dsi0 init finished
[400] [DISP]func|ddp_dsi_config
[400] [DISPCHECK][DDPDSI] DSI Mode: SYNC_EVENT_VDO_MODE
[400] [DISPCHECK][DDPDSI] LANE_NUM: 4,data_format: 0,vertical_sync_active: 0
[400] [DISPCHECK][DDPDSI] vact: 10, vbp: 23, vfp: 12, vact_line: 600, hact: 10, hbp: 160, hfp: 160, hblank: 0, hblank: 1105566796
[400] [DISPCHECK][DDPDSI] pll_select: 0, pll_div1: 0, pll_div2: 0, fbk_div: 0,fbk_sel: 0, rg_bir: 0
[400] [DISPCHECK][DDPDSI] rg_bic: 0, rg_bp: 0, PLL_CLOCK: 175, dsi_clock: 0, ssc_range: 0, ssc_disable: 0, compatibility_for_nvk: 0, cont_clock: 0
[400] [DISPCHECK][DDPDSI] lcm_ext_te_enable: 0, noncont_clock: 0, noncont_clock_period: 0
[400] [DISP]func|DSI_PHY_clk_setting
[400] [DISP][mipitx/inreg]0x10206190=0x00000000
[400] [DISP][mipitx/reg]0x14017004=0x00000020
[400] [DISP][mipitx/reg]0x14017014=0x00000000
[400] [DISP][mipitx/reg]0x14017010=0x00000000
[420] [DISP][mipitx/reg]0x1401700c=0x00000000
[420] [DISP][mipitx/reg]0x14017008=0x00000000
[420] [DISP]PLL config: LNT=0x0,clk=0x20,lan3=0x20,lan2=0x0,lan1=0x0,lan0=0x0
[420] [DISP][mipitx/reg]0x14017044=0x88492481
[420] [DISP][mipitx/reg]0x14017044=0x88492483
[420] [DISP][mipitx/reg]0x14017040=0x00000882
[420] [DISP][mipitx/reg]0x14017000=0x00000402
[420] [DISP][mipitx/reg]0x14017000=0x00000403
[420] [DISP][mipitx/reg]0x14017068=0x00000003
[420] [DISP][mipitx/reg]0x14017068=0x00000101
[420] [DISP][mipitx/reg]0x14017050=0x00000008
[420] [DISP][mipitx/reg]0x14017050=0x00000008
[420] [DISP][mipitx/reg]0x14017050=0x00000008
[420] [DISP][mipitx/reg]0x14017054=0x00000001
[420] [DISP][mipitx/reg]0x14017058=0x35000000
[420] [DISP][mipitx/reg]0x14017058=0x35d80000
[420] [DISP][mipitx/reg]0x14017058=0x35d89d00
[420] [DISP][mipitx/reg]0x14017058=0x35d89d89
[420] [DISP][mipitx/reg]0x14017054=0x00000003
[440] [DISP][mipitx/reg]0x14017054=0x01b10003
[440] [DISP][mipitx/reg]0x1401705c=0x065d065d
[440] [DISP][mipitx/reg]0x1401705c=0x065d065d
[440] [DISP][dsi_drv.c] PLL config:data_rate=350,txdiv=2,pcw=903388553,delta1=5,pdelta1=0x65d
[440] [DISP][mipitx/reg]0x14017054=0x01b10007
[440] [DISP][mipitx/reg]0x14017004=0x00000021
[440] [DISP][mipitx/reg]0x14017008=0x00000001
[440] [DISP][mipitx/reg]0x1401700c=0x00000001
[440] [DISP][mipitx/reg]0x14017010=0x00000001
[440] [DISP][mipitx/reg]0x14017014=0x00000001
[440] [DISP][mipitx/reg]0x14017050=0x00000009
[440] [DISP][mipitx/reg]0x14017060=0x00000000
[440] [DISP][mipitx/reg]0x14017060=0x00000001
[440] [DISP][mipitx/reg]0x14017040=0x00000082
[440] DISP/[DISP] - kernel - DSI_PHY_TIMCONFIG, Cycle Time = 23(ns), Unit Interval = 3(ns). , lane# = 4
[440] DISP/[DISP] - kernel - DSI_PHY_TIMCONFIG, HS_TRAIL = 4, HS_ZERO = 7, HS_PRPR = 3, LPX = 3, TA_GET = 15, TA_SURE = 4, TA_GO = 12, CLK_TRAIL = 5,
[460] [DISP]func|disp_lcm_init
===================== lcm_gpio_set 152: num:78 => 1 =======================
===================== lcm_gpio_set 152: num:147 => 1 =======================
[IND][K] y_____0init_lcm_registers
[740] [DISP]func|DSI_set_cmdq
[740] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[740] [DISP]func|DSI_set_cmdq
[740] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[740] [DISP]func|DSI_set_cmdq
[740] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[740] [DISP]func|DSI_set_cmdq
[740] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[740] [DISP]func|DSI_set_cmdq
[740] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[760] [DISP]func|DSI_set_cmdq
[760] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[760] [DISP]func|DSI_set_cmdq
[760] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[860] [DISP]func|DSI_dcs_read_lcm_reg_v2
[860] DISP/ Start polling DSI read ready！
[860] DISP/ End polling DSI read ready！
[860] [DISP]DSI_CMDQ_SIZE : 0x1
[860] [DISP]DSI_CMDQ_DATA0 : 0x4
[860] [DISP]DSI_CMDQ_DATA1 : 0x6
[860] [DISP]DSI_CMDQ_DATA2 : 0xa
[860] [DISP]DSI_CMDQ_DATA3 : 0x0
[860] [DISP]DSI_RX_DATA0 : 0x12000021
[860] [DISP]DSI_RX_DATA1 : 0x10f0f08
[860] [DISP]DSI_RX_DATA2 : 0x0
[860] [DISP]DSI_RX_DATA3 : 0x0
[860] [DISP]read_data0, 21,0,0,12
[860] [DISP]read_data1, 8,f,f,1
[880] [DISP]read_data2, 0,0,0,0
[880] [DISP]read_data3, 0,0,0,0
[880] DISP/ DSI read packet_type is 0x21
[880] [DISP]lcm is connected
[880] [DISP]func|disp_lcm_is_video_mode
[880] [DISP]func|primary_display_config_input
[880] [DISP]func|ddp_dsi_is_busy
[880] [DISP]func|ddp_dsi_config
[880] [DISP]func|primary_display_config_input
[880] [DISP]func|ddp_dsi_is_busy
[880] [DISP]func|ddp_dsi_config
[880] mt_get_logo_db_addr: 0x7f370000
[920] fb dump: 0x00000000, 0x00000000, 0x00000000, 0x00000000
[940] [DISP]func|primary_display_trigger
[940] [DISP]func|ddp_dsi_is_busy
[940] [DISPCHECK]trigger mode: DIRECT_LINK
[940] [DISP]func|disp_lcm_is_video_mode
[940] [DISP]func|disp_lcm_is_video_mode
[940] s_mt65xx_gd.gdfIndex=3[940] mt_get_logo_db_addr_pa: 0x7f370000
[940] [PART_LK][get_part] logo
[940] [PART_LK][get_part] logo
=========================================
[940] [LK_BOOT] logo magic number : 0x58881688
[940] [LK_BOOT] logo name : LOGO
[940] [LK_BOOT] logo size : 802341
=========================================
read the data of logo
kedump mini start
kedump: boot_reason(1)
RAM_CONSOLE. sram(0x12c000) sig 0 mismatch
RAM_CONSOLE. start: 0x43f00000, size: 0x10000
RAM_CONSOLE. lk size mismatch 0 + c0 ！= 100
[980] D:No boot record found at 0x41f00000[0000]
[980] detecting pmic just reset
[mboot_recovery_load_misc]: size is 6144
[mboot_recovery_load_misc]: misc_addr is 0x41e6d548
[980] [PART_LK][get_part] para
[980] [LK_BOOT] Load '<null>' partition to 0x41E6D548 (6144 bytes in 2 ms)
[980] MT65XX_FACTORY_KEY 0x0
[980] MT65XX_BOOT_MENU_KEY 0x11
[980] MT65XX_RECOVERY_KEY 0x11
[980] mtk detect key function key = 0
[980] mtk detect key function key = 17
[980] mtk detect key function key = 17
[980] mtk detect key function key = 0
[980] mtk detect key function key = 17
[980] mtk detect key function key = 17
[980] mtk detect key function key = 0
[980] mtk detect key function key = 17
[980] mtk detect key function key = 17
[1000] mtk detect key function key = 0
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 0
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 0
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 0
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 0
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 0
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 0
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 0
[1010] mtk detect key function key = 17
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 0
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 0
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 0
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 0
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 0
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 0
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 0
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 17
[1040] mtk detect key function key = 0
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 0
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 0
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 0
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 0
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 0
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 0
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 0
[1040] mtk detect key function key = 17
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 0
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 0
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 0
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 0
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 0
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 0
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 0
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 17
[1070] mtk detect key function key = 0
[1080] mtk detect key function key = 17
[1080] mtk detect key function key = 17
[1080] mtk detect key function key = 0
[1080] mtk detect key function key = 17
[1080] mtk detect key function key = 17
[1080] mtk detect key function key = 0
[1080] mtk detect key function key = 17
[1080] mtk detect key function key = 17
[1080] mtk detect key function key = 0
[1080] mtk detect key function key = 17
[1080] mtk detect key function key = 17
[LK_ENV]get_env off-mode-charge
[1080] [upmu_is_chr_det] 1
< Kernel Power Off Charging Detection Ok>
[1080] [AUXADC] ch=0 raw=24501 data=4037
[1080] [mt65xx_bat_init] check VBAT=4037 mV with 3450 mV
[1080] [upmu_is_chr_det] 1
[1080] mt_get_logo_db_addr: 0x7f370000
[1080] mt_get_tempfb_addr: 0x7fc30000
[1180] fb dump: 0x00000000, 0xff000000, 0xff000000, 0xff0000
[USBD] USB PRB0 LineState: 0
[USBD] USB cable/ No Cable inserted！
[PLFM] Keep stay in USB Mode
[PWRAP] pwrap_init_preloader
[PWRAP] pwrap_init
[PWRAP] start reset wrapper
[PWRAP] the reset register =80
[PWRAP] PMIC_WRAP_STAUPD_GRPEN =0x0,it should be equal to 0xc
[PWRAP] _pwrap_init_reg_clock
[PWRAP] have cipher
[PWRAP] _pwrap_init_signature
[PWRAP] mt_pwrap_init PMIC_WRAP_STAUPD_GRPEN(3D)
[PWRAP] mt_pwrap_init-- use D1 or D3
[PWRAP] mt_pwrap_init---- debug15,FFFFFBFF
[PWRAP] after MT6328 pwrap_write
[PWRAP] write MT6328 Test pass
[PWRAP] Read 6328 Test pass,return_value=0
[PMIC_WRAP]wrap_init pass,the return value=0.
[pmic_init] Preloader Start..................
[pmic_init] MT6328 CHIP Code = 0x2820
bat is exist
[pmic_init] turn off usbdl wo Battery..................
just_rst = 0
[6328] is_efuse_trimed=0x1,[0xC5C]=0x8000
[6328] efuse_data[0x0]=0x0
[6328] efuse_data[0x1]=0xD144
[6328] efuse_data[0x2]=0xD144
[6328] efuse_data[0x3]=0xFBEF
[6328] efuse_data[0x4]=0xFBEF
[6328] efuse_data[0x5]=0x4400
[6328] efuse_data[0x6]=0x4400
[6328] efuse_data[0x7]=0x400
[6328] efuse_data[0x8]=0x400
[6328] efuse_data[0x9]=0x643C
[6328] efuse_data[0xA]=0x643C
[6328] efuse_data[0xB]=0x0
[6328] efuse_data[0xC]=0x0
[6328] efuse_data[0xD]=0x74
[6328] efuse_data[0xE]=0x0
[6328] efuse_data[0xF]=0x0
[6328] efuse_data[0x10]=0x0
[6328] efuse_data[0x11]=0x0
[6328] efuse_data[0x12]=0x0
[6328] efuse_data[0x13]=0x0
[6328] efuse_data[0x14]=0x0
[6328] efuse_data[0x15]=0x0
[6328] efuse_data[0x16]=0x0
[6328] efuse_data[0x17]=0x0
[6328] efuse_data[0x18]=0x0
[6328] efuse_data[0x19]=0x0
[6328] efuse_data[0x1A]=0x0
[6328] efuse_data[0x1B]=0x0
[6328] efuse_data[0x1C]=0x0
[6328] efuse_data[0x1D]=0x0
[6328] efuse_data[0x1E]=0x0
[6328] efuse_data[0x1F]=0x0
[upmu_set_rg_vio18_184] old cal=0 new cal=14.
[pmic_init] Reg[0x2A0]=0X301
[pmic_init] Done...................
[mmc_init]: msdc0 start mmc_init_host() in PL...
[msdc_init]: msdc0 Host controller intialization start
[MSDC]config VEMC to 3V in preloader
[SD0] Pins mode(1), none(0), down(1), up(2), keep(3)
[SD0] Pins mode(2), none(0), down(1), up(2), keep(3)
[MSDC]config VEMC to 3V in preloader
[info][msdc_set_startbit 1242] read data start bit at rising edge
[info][msdc_config_clksrc] input clock is 400000kHz
[SD0] Bus Width: 1
[info][msdc_config_clksrc] input clock is 400000kHz
[info][msdc_set_startbit 1242] read data start bit at rising edge
[SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) div(385) DS(0) RS(0)
[msdc_init]: msdc0 Host controller intialization done
[mmc_init]: msdc0 start mmc_init_card() in PL...
[mmc_init_card]: start
[info][msdc_config_clksrc] input clock is 400000kHz
[info][msdc_set_startbit 1242] read data start bit at rising edge
[SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) div(385) DS(0) RS(0)
[SD0] Bus Width: 8
[SD0] Switch to High-Speed mode！
[info][msdc_config_clksrc] input clock is 400000kHz
[info][msdc_set_startbit 1242] read data start bit at rising edge
[SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(2) DDR(1) div(192) DS(0) RS(0)
[SD0] Bus Width: 8
[SD0] Size: 7456 MB, Max.Speed: 52000 kHz, blklen(512), nblks(15269888), ro(0)
[mmc_init_mem_card 3144][SD0] Initialized, eMMC50
before host->cur_bus_clk(259740)
[info][msdc_config_clksrc] input clock is 400000kHz
[info][msdc_set_startbit 1242] read data start bit at rising edge
[SD0] SET_CLK(52000kHz): SCLK(50000kHz) MODE(2) DDR(1) div(1) DS(0) RS(0)
host->cur_bus_clk(50000000)
[mmc_init_card]: finish successfully
[EMI] mcp_dram_num:2,discrete_dram_num:0,enable_combo_dis:0
[EMI] index(0) emmc id match failed
found:1,i:1
[PLFM] Init I2C: OK(0)
[PLFM] Init PWRAP: OK(0)
[PLFM] Init PMIC: OK(0)
[PLFM] chip_code[321]
[PLFM] chip_ver[0]
[PTP] >> ptp_init()
[PTP] >> get_devinfo()
[PTP] << get_devinfo():322
[PTP] >> ptp_init_det()
[PTP] VCORE voltage bin to 1.05V
[PTP] << ptp_init_det():444
[PTP] PTP set volt: 0x00000048
[PTP] 0x00000057
[PTP] 0x00000056
[PTP] 0x00000055
[PTP] 0x00000054
[PTP] 0x00000053
[PTP] 0x00000052
[PTP] 0x00000051
[PTP] 0x00000050
[PTP] 0x0000004F
[PTP] 0x0000004E
[PTP] 0x0000004D
[PTP] 0x0000004C
[PTP] 0x0000004B
[PTP] 0x0000004A
[PTP] 0x00000049
[PTP] 0x00000048
[PTP] M_HW_RES0 = 0x10D13A34
[PTP] M_HW_RES1 = 0x006A0000
[PTP] M_HW_RES2 = 0x00000006
[PTP] M_HW_RES3 = 0x00364EE3
[PTP] M_HW_RES4 = 0x00000000
[PTP] M_HW_RES5 = 0x00000003
[PTP] << ptp_init():1032
[BLDR] Build Time: 20150323-203315
[DDR Reserve] ddr reserve mode not be enabled yet
RGU rgu_release_rg_dramc_conf_iso:mtk_WDT_DEBUG_CTL(590200F1)
RGU rgu_release_rg_dramc_iso:MTK_WDT_DEBUG_CTL(590200F1)
RGU rgu_release_rg_dramc_sref:MTK_WDT_DEBUG_CTL(590200F1)
DDR is in self-refresh. 200F1
DDR is in self-refresh. 200F1
DDR is in self-refresh. 200F1
==== Dump RGU Reg ========
RGU MODE: 4D
RGU LENGTH: FFE0
RGU STA: 0
RGU INTERVAL: FFF
RGU SWSYSRST: 8000
==== Dump RGU Reg End ====
RGU: g_rgu_satus:0
mtk_wdt_mode_config mode value=10, tmp:22000010
PL P ON
WDT does not trigger reboot
mtk_wdt_mode_config mode value=5D, tmp:2200005D
WDT NONRST=0X20000000
WDT IRQ_EN=0x340002
WDT REQ_EN=0x3C0002
RGU mtk_wdt_init:MTK_WDT_DEBUG_CTL(590200F3)
Enter mtk_kpd_GPIO_set！
after set KP enable: KP_SEL = 0x0 ！
[RTC] get_frequency_meter: input=0x0, ouput=5
[RTC] get_frequency_meter: input=0x0, ouput=3967
[RTC] get_frequency_meter: input=0x0, ouput=5
[RTC] get_frequency_meter: input=0x0, ouput=0
[RTC] get_frequency_meter: input=0x0, ouput=0
[RTC] bbpu = 0x1, con = 0x84A7, osc32con = 0x7B00, sec = 0x21BF, yea = 0x2
rtc_first_boot_init
[RTC] get_frequency_meter: input=0x0, ouput=5
[RTC] get_frequency_meter: input=0x0, ouput=3967
[RTC] get_frequency_meter: input=0x0, ouput=5
[RTC] get_frequency_meter: input=0x0, ouput=0
[RTC] get_frequency_meter: input=0x0, ouput=0
OSC32CON_ANALOG_SETTING = 0x7B00
rtc_2sec_stat_clear
rtc_2sec_reboot_check 0x21BF
rtc_2sec_stat_clear
[RTC] irqsta = 0x0, pdn1 = 0x0, pdn2 = 0x201, spar0 = 0xC0, spar1 = 0x800
[RTC] new_spare0 = 0x0, new_spare1 = 0x1, new_spare2 = 0x1, new_spare3 = 0x1
[RTC] bbpu = 0x1, con = 0x4A6, cali = 0x21BF
pl pmic powerkey Release
[pmic_IsUsbCableIn] 1
[PLFM] USB/charger boot！
[RTC] rtc_bbpu_power_on done
mt_get_dram_type() 0x3
[EMI] LPDDR3
[Check]mt_get_mdl_number 0x1
[EMI] eMMC/NAND ID = 15,1,0,51,37,32,53,4D,42,0,E5,D6,C6,2A,C1,85
[EMI] MDL number = 1
[EMI] emi_set eMMC/NAND ID = 15,1,0,51,37,32,53,4D,42,0,0,0,0,0,0,0
Start REXTDN SW calibration...
enable P drive (initial settings), 0x0644:27Dh
2.1. DRVP 0x00c0[15:12]:0h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:1000h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:2000h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:3000h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:4000h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:5000h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:6000h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:7000h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:8000h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:9000h
2.2. CMPOP 0x03dc[31]:0h
2.1. DRVP 0x00c0[15:12]:A000h
2.2. CMPOP 0x03dc[31]:80000000h
P drive:10
enable N drive (initial settings), 0x0644:17Dh
4.1. DRVN 0x00c0[11:8]:A000h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:A100h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:A200h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:A300h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:A400h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:A500h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:A600h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:A700h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:A800h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:A900h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:AA00h
4.2.CMPON 0x3dc[30]:0h
4.1. DRVN 0x00c0[11:8]:AB00h
4.2.CMPON 0x3dc[30]:40000000h
N drive:10
drvp=10,drvn=10
=============================================
X-axis: DQS Gating Window Delay (Fine Scale)
Y-axis: DQS Gating Window Delay (Coarse Scale)
=============================================
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
--------------------------------------------------------------------------------
0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0010:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0011:| 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0012:| 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
0013:| 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0
0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rank 0 coarse tune value selection : -404,
rank 0 coarse = 18
rank 0 fine = 56
==============================================================
DATLAT calibration
==============================================================
DATLAT Default value = 0x8
TAP=0, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=1, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=2, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=3, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=4, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=5, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=6, err_value=0xFBFF7AFF, begin=0, first=255, sum=0
TAP=7, err_value=0x0, begin=1, first=7, sum=1
TAP=8, err_value=0x0, begin=1, first=7, sum=2
TAP=9, err_value=0x0, begin=1, first=7, sum=3
TAP=10, err_value=0x0, begin=1, first=7, sum=4
TAP=11, err_value=0x0, begin=1, first=7, sum=5
TAP=12, err_value=0x0, begin=1, first=7, sum=6
TAP=13, err_value=0x0, begin=1, first=7, sum=7
TAP=14, err_value=0x0, begin=1, first=7, sum=8
TAP=15, err_value=0x0, begin=1, first=7, sum=9
first_step=7 total pass=9 best_step=8
=============================================
X-axis: DQS Gating Window Delay (Fine Scale)
Y-axis: DQS Gating Window Delay (Coarse Scale)
=============================================
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
--------------------------------------------------------------------------------
0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0010:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
0011:| 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0012:| 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
0013:| 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0
0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rank 1 coarse tune value selection : -404,
rank 1 coarse = 18
rank 1 fine = 56
==============================================================
DATLAT calibration
==============================================================
DATLAT Default value = 0x8
TAP=0, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=1, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=2, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=3, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=4, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=5, err_value=0xFFFFFFFF, begin=0, first=255, sum=0
TAP=6, err_value=0xB9FFFAF7, begin=0, first=255, sum=0
TAP=7, err_value=0x0, begin=1, first=7, sum=1
TAP=8, err_value=0x0, begin=1, first=7, sum=2
TAP=9, err_value=0x0, begin=1, first=7, sum=3
TAP=10, err_value=0x0, begin=1, first=7, sum=4
TAP=11, err_value=0x0, begin=1, first=7, sum=5
TAP=12, err_value=0x0, begin=1, first=7, sum=6
TAP=13, err_value=0x0, begin=1, first=7, sum=7
TAP=14, err_value=0x0, begin=1, first=7, sum=8
TAP=15, err_value=0x0, begin=1, first=7, sum=9
first_step=7 total pass=9 best_step=8
DQS loop = 15, cmp_err_1 = 0
DQS loop = 14, cmp_err_1 = 0
DQS loop = 13, cmp_err_1 = 0
DQS loop = 12, cmp_err_1 = 0
DQS loop = 11, cmp_err_1 = 0
DQS loop = 10, cmp_err_1 = 0
DQS loop = 9, cmp_err_1 = 0
DQS loop = 8, cmp_err_1 = 0
DQS loop = 7, cmp_err_1 = 0
DQS loop = 6, cmp_err_1 = 0
DQS loop = 5, cmp_err_1 = 0
DQS loop = 4, cmp_err_1 = 0
DQS loop = 3, cmp_err_1 = 0
DQS loop = 2, cmp_err_1 = 0
DQS loop = 1, cmp_err_1 = 0
DQS loop = 0, cmp_err_1 = 0
DQ loop=15, cmp_err_1 = F020A00
DQ loop=14, cmp_err_1 = A000A00
DQ loop=13, cmp_err_1 = 2000800
DQ loop=12, cmp_err_1 = 800
DQ loop=11, cmp_err_1 = 0
DQ loop=10, cmp_err_1 = 0
DQ loop=9, cmp_err_1 = 0
DQ loop=8, cmp_err_1 = 0
DQ loop=7, cmp_err_1 = 0
DQ loop=6, cmp_err_1 = 0
DQ loop=5, cmp_err_1 = 0
DQ loop=4, cmp_err_1 = 0
DQ loop=3, cmp_err_1 = 0
DQ loop=2, cmp_err_1 = 0
DQ loop=1, cmp_err_1 = 0
DQ loop=0, cmp_err_1 = 0
byte:0, (DQS,DQ)=(0,0)
byte:1, (DQS,DQ)=(2,0)
byte:2, (DQS,DQ)=(0,0)
byte:3, (DQS,DQ)=(1,0)
[EMI] DRAMC calibration passed
[DRAM] DFS rank0 coarse fine : 18 56, rank1 coarse fine :18 56
DFS could be enable
[MEM] complex R/W mem test pass
RGU rgu_dram_reserved:MTK_WDT_MODE(220000DD)
[Dram_Buffer] dram_buf_t size: 0x1998C0
[Dram_Buffer] part_hdr_t size: 0x200
[Dram_Buffer] sizeof(boot_arg_t): 0x168
[Dram_Buffer] g_dram_buf start addr: 0x42000000
[Dram_Buffer] g_dram_buf->msdc_gpd_pool start addr: 0x42199800
[Dram_Buffer] g_dram_buf->msdc_bd_pool start addr: 0x4���ӗ��}��[�A
� ���u�#NTLuFd sram(0x4B1D8D57) sig mismatch���g�X'H
RAM_CONSOLE start: 0x43F00000, size: 0x10000, sig: 0x40040000
RAM_CONSOLE wdt status (0x43F00040)=0x0
[PLFM] Init Boot Device: OK(0)
Enter mtk_kpd_gpio_set！
mtk detect key function pmic_detect_homekey MTK_PMIC_RST_KEY = 17
pl pmic FCHRKEY Release
0:dram_rank_size:20000000
1:dram_rank_size:20000000
0:dram_rank_size:20000000
1:dram_rank_size:20000000
orig_dram_info[0] start: 0x0000000040000000, size: 0x0000000020000000
orig_dram_info[1] start: 0x0000000060000000, size: 0x0000000020000000
CUSTOM_CONFIG_MAX_DRAM_SIZE: 0x0000000100000000
total_dram_size: 0x0000000040000000, max_dram_size: 0x0000000100000000
�����������[GPT_PL]Parsing Primary GPT now...
[GPT_PL][0]name=proinfo, part_id=8, start_sect=0x400, nr_sects=0x1800
[GPT_PL][1]name=nvram, part_id=8, start_sect=0x1C00, nr_sects=0x2800
[GPT_PL][2]name=protect1, part_id=8, start_sect=0x4400, nr_sects=0x5000
[GPT_PL][3]name=protect2, part_id=8, start_sect=0x9400, nr_sects=0x5000
[GPT_PL][4]name=lk, part_id=8, start_sect=0xE400, nr_sects=0x400
[GPT_PL][5]name=para, part_id=8, start_sect=0xE800, nr_sects=0x400
[GPT_PL][6]name=boot, part_id=8, start_sect=0xEC00, nr_sects=0x8000
[GPT_PL][7]name=recovery, part_id=8, start_sect=0x16C00, nr_sects=0x8000
[GPT_PL][8]name=logo, part_id=8, start_sect=0x1EC00, nr_sects=0x4000
[GPT_PL][9]name=expdb, part_id=8, start_sect=0x22C00, nr_sects=0x5000
[GPT_PL][10]name=seccfg, part_id=8, start_sect=0x27C00, nr_sects=0x400
[GPT_PL][11]name=oemkeystore, part_id=8, start_sect=0x28000, nr_sects=0x1000
[GPT_PL][12]name=secro, part_id=8, start_sect=0x29000, nr_sects=0x3000
[GPT_PL][13]name=keystore, part_id=8, start_sect=0x2C000, nr_sects=0x4000
[GPT_PL][14]name=tee1, part_id=8, start_sect=0x30000, nr_sects=0x2800
[GPT_PL][15]name=tee2, part_id=8, start_sect=0x32800, nr_sects=0x2800
[GPT_PL][16]name=frp, part_id=8, start_sect=0x35000, nr_sects=0x800
[GPT_PL][17]name=nvdata, part_id=8, start_sect=0x35800, nr_sects=0x10000
[GPT_PL][18]name=metadata, part_id=8, start_sect=0x45800, nr_sects=0x12800
[GPT_PL][19]name=system, part_id=8, start_sect=0x58000, nr_sects=0x300000
[GPT_PL][20]name=cache, part_id=8, start_sect=0x358000, nr_sects=0xC8000
[GPT_PL][21]name=userdata, part_id=8, start_sect=0x420000, nr_sects=0xA67C00
[GPT_PL][22]name=flashinfo, part_id=8, start_sect=0xE87C00, nr_sects=0x8000
[GPT_PL]Success to find valid GPT.
[PART] blksz: 512B
[PART] [0x0000000000080000-0x000000000037FFFF] "proinfo" (6144 blocks)
[PART] [0x0000000000380000-0x000000000087FFFF] "nvram" (10240 blocks)
[PART] [0x0000000000880000-0x000000000127FFFF] "protect1" (20480 blocks)
[PART] [0x0000000001280000-0x0000000001C7FFFF] "protect2" (20480 blocks)
[PART] [0x0000000001C80000-0x0000000001CFFFFF] "lk" (1024 blocks)
[PART] [0x0000000001D00000-0x0000000001D7FFFF] "para" (1024 blocks)
[PART] [0x0000000001D80000-0x0000000002D7FFFF] "boot" (32768 blocks)
[PART] [0x0000000002D80000-0x0000000003D7FFFF] "recovery" (32768 blocks)
[PART] [0x0000000003D80000-0x000000000457FFFF] "logo" (16384 blocks)
[PART] [0x0000000004580000-0x0000000004F7FFFF] "expdb" (20480 blocks)
[PART] [0x0000000004F80000-0x0000000004FFFFFF] "seccfg" (1024 blocks)
[PART] [0x0000000005000000-0x00000000051FFFFF] "oemkeystore" (4096 blocks)
[PART] [0x0000000005200000-0x00000000057FFFFF] "secro" (12288 blocks)
[PART] [0x0000000005800000-0x0000000005FFFFFF] "keystore" (16384 blocks)
[PART] [0x0000000006000000-0x00000000064FFFFF] "tee1" (10240 blocks)
[PART] [0x0000000006500000-0x00000000069FFFFF] "tee2" (10240 blocks)
[PART] [0x0000000006A00000-0x0000000006AFFFFF] "frp" (2048 blocks)
[PART] [0x0000000006B00000-0x0000000008AFFFFF] "nvdata" (65536 blocks)
[PART] [0x0000000008B00000-0x000000000AFFFFFF] "metadata" (75776 blocks)
[PART] [0x000000000B000000-0x000000006AFFFFFF] "system" (3145728 blocks)
[PART] [0x000000006B000000-0x0000000083FFFFFF] "cache" (819200 blocks)
[PART] [0x0000000084000000-0x00000001D0F7FFFF] "userdata" (10910720 blocks)
[PART] [0x00000001D0F80000-0x00000001D1F7FFFF] "flashinfo" (32768 blocks)
[ROM_INFO] 'v2','0x0','0x0','0x0','0x2C00'
[SEC_K] SML KEY AC = 0
[SEC_K] SBC_PUBK Found
[SEC] AES Legacy : 0
[SEC] SECCFG AC : 1
[LIB] Loading SEC config
[LIB] Name =
[LIB] Config = 0x22, 0x22
[LIB] SECRO (ac, ac_offset, ac_length) = (0x1, 0x40, 0x40)
0x31,0x41,0x35,0x35
[SEC] DBGPORT (0 1)
[SEC] read '0x4F80000'
0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,
[LIB] CFG read size '0x2000' '0x1860'
0x0
[LIB] HW DEC
0x170A9D79
[LIB] SEC CFG doesn't exist
[SEC] init fail '0x3000'
[LIB] seccfg magic is incorrect
[PLFM] USB cable in
[TOOL] USB enum timeout (Yes), handshake timeout(Yes)
[USBD] USB Full Speed
[TOOL] Enumeration(Start)
[USBD] USB High Speed
[USBD] USB High Speed
[TOOL] Enumeration(End): OK 401ms
usbdl_flush timeout
usbdl_flush timeout
[TOOL] : usb listen timeout
[TOOL] <USB> cannot detect tools！
[TOOL] <UART> listen ended, receive size:0！
[TOOL] <UART> wait sync time 150ms->5ms
[TOOL] <UART> receieved data: ()
[LIB] NS-CHIP
[SBC] Don't check
Device APC domain init setup:
Domain Setup (0x0)
Domain Setup (0x0)
Domain Setup (0x0)
Device APC domain after setup:
Domain Setup (0x0)
Domain Setup (0x1020000)
warning: size is not 2MB aligned
mblock[0].start: 0x0000000040000000, sz: 0x0000000020000000, limit: 0x0000000100000000, max_addr: 0x0000000000000000, max_rank: 1, target: -1, mblock[0
mblock_reserve dbg[0]: 1, 1, 1, 1
mblock[1].start: 0x0000000060000000, sz: 0x0000000020000000, limit: 0x0000000100000000, max_addr: 0x0000000060000000, max_rank: 1, target: 0, mblock[]1
mblock_reserve dbg[1]: 1, 1, 1, 1
mblock_reserve: 000000007FFC0000 - 0000000080000000 from mblock 1
[PART] Image with part header
[PART] name : LK
[PART] addr : FFFFFFFFh mode : -1
[PART] size : 308556
[PART] magic: 58881688h
[PART] load "lk" from 0x0000000001C80200 (dev) to 0x41E00000 (mem) [SUCCESS]
[PART] load speed: 50220KB/s, 308556 bytes, 6ms
[PART] Image with part header
[PART] name : ATF
[PART] addr : FFFFFFFFh mode : 0
[PART] size : 53248
[PART] magic: 58881688h
[PART] load "tee1" from 0x0000000006000200 (dev) to 0x43000DC0 (mem) [SUCCESS]
[PART] load speed: 13000KB/s, 53248 bytes, 4ms
[TZ_INIT] tee_verify_image : passed
[BLDR] bldr load tee part ret=0x0, addr=0x43001000
[BLDR] part_load_raw_part ret=0x0
[BLDR] part_load_images ret=0x0
bat is exist
[pmic_init] turn off usbdl wo battery..................
[PLFM],64S3,boot_opt=0x0
[PLFM],32N2,boot_opt=0x6
[PLFM],64N2,boot_opt=0x4
[PLFM] boot to LK by ATAG.
boot reason: 1
boot mode: 0
META COM0: 0
rank[0] size: 0x20000000
rank[1] size: 0x1FFC0000
tee reserved mem: 0x000000007FFC0000, 0x0000000000040000
md_type[0]: 0x0
md_type[1]: 0x0
boot time: 4664
DDR reserve mode: enable = 0, success = 0
dram buffer size: 1677504
[PTP][preloader]first_volt = 0x68
[PTP][preloader]second_volt = 0x48
[PTP][preloader]third_volt = 0x48
[PTP][preloader]have_550 = 0x0
SMC: 0x0
LK: 0x6
KERNEL: 0x4
NONSEC SRAM Addr: 0x10DC00
NONSEC SRAM Size: 0x2400
[TZ_INIT] hwuid[0] : 0x1B4DFAF8
[TZ_INIT] hwuid[1] : 0xCCE7DB22
[TZ_INIT] hwuid[2] : 0x434CB0D0
[TZ_INIT] hwuid[3] : 0x20922011
[TZ_INIT] HRID[0] : 0xE6FE37C6
[TZ_INIT] HRID[1] : 0xD7C9C7CB
[TZ_INIT] atf_log_port : 0x11002000
[TZ_INIT] atf_log_baudrate : 0xE1000
[TZ_INIT] atf_irq_num : 281
[TZ_INIT] ATF log buffer start : 0x7FFC0000
[TZ_INIT] ATF log buffer size : 0x40000
[TZ_INIT] ATF aee buffer start : 0x7FFFC000
[TZ_INIT] ATF aee buffer size : 0x4000
[BLDR] Others, jump to ATF
[BLDR] jump to 0x41E00000
[BLDR] <0x41E00000>=0xEA000007
[BLDR] <0x41E00004>=0xEA005B99
[TZ_SEC_CFG] SRAMROM Secure Addr 0xDC00
[TZ_SEC_CFG] SRAMROM Secure Control 0x0
[TZ_SEC_CFG] SRAMROM Secure Control 0xB69
[TZ_SEC_CFG] SRAMROM Secure Control 0x1B680B69
[TZ_INIT] ATF entry addr, aligned addr : 0x43001000, 0x43000000
[TZ_EMI_MPU] MPU [0x43000000-0x4302FFFF]
[TZ_INIT] set secure memory protection : 0x43000000, 0x4302FFFF (1)
[TZ_INIT] Jump to ATF, then 0x41E00000
[ATF][ 0.000000]BL33 boot argument location=0x42199880
[ATF][ 0.000000]BL33 boot argument size=0x168
[ATF][ 0.000000]BL33 start addr=0x41e00000
[ATF][ 0.000000]teearg addr=0x101000
[ATF][ 0.000000]atf_magic=0x4d415446
[ATF][ 0.000000]tee_support=0x0
[ATF][ 0.000000]tee_entry=0x0
[ATF][ 0.000000]tee_boot_arg_addr=0x101100
[ATF][ 0.000000]atf_log_port=0x11002000
[ATF][ 0.000000]atf_log_baudrate=0xe1000
[ATF][ 0.000000]atf_log_buf_start=0x7ffc0000
[ATF][ 0.000000]atf_log_buf_size=0x40000
[ATF][ 0.000000]atf_aee_debug_buf_start=0x7fffc000
[ATF][ 0.000000]atf_aee_debug_buf_size=0x4000
[ATF][ 0.000000]atf_irq_num=281
[ATF][ 0.000000]BL33_START_ADDRESS=0x41e00000
[ATF][ 0.000000]###@@@ MP0_MISC_CONFIG3:0x00000000 @@@###
[ATF][ 0.000000]###@@@ MP0_MISC_CONFIG3:0x0000e000 @@@###
[ATF][ 0.000000]mmap atf buffer : 0x7ffc0000, 0x40000
[ATF][ 0.000000]mmap atf buffer (force 2MB aligned): 0x7fe00000, 0x200000
NOTICE: BL3-1: v1.0(debug):e7d64d4
NOTICE: BL3-1: Built : 10:50:39, Mar 21 2015
[ATF][ 0.000000]sta=0x0 int=0xffc
[ATF][ 0.000000]is_power_on_boot: true
[ATF][ 0.000000]mt_log_setup - atf_buf_addr : 0x7ffc0100
[ATF][ 0.000000]mt_log_setup - atf_buf_size : 0x2bf00
[ATF][ 0.000000]mt_log_setup - atf_write_pos : 0x7ffc0100
[ATF][ 0.000000]mt_log_setup - atf_read_pos : 0x7ffc0100
[ATF][ 0.000000]mt_log_setup - atf_buf_lock : 0x0
[ATF][ 0.000000]mt_log_setup - mt_log_buf_end : 0x7ffebfff
[ATF][ 0.000000]mt_log_setup - ATF_CRASH_LAST_LOG_SIZE : 0x8000
[ATF][ 0.000000]mt_log_setup - ATF_EXCEPT_BUF_SIZE_PER_CPU : 0x1000
[ATF][ 0.000000]mt_log_setup - ATF_EXCEPT_BUF_SIZE : 0x8000
[ATF][ 0.000000]mt_log_setup - PLATFORM_CORE_COUNT : 0x8
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[0]: 0x7fff4000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[1]: 0x7fff5000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[2]: 0x7fff6000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[3]: 0x7fff7000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[4]: 0x7fff8000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[5]: 0x7fff9000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[6]: 0x7fffa000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[7]: 0x7fffb000
[ATF][ 0.000000]mt_log_setup - atf_crash_flag : 0x0
[ATF][ 0.000000]mt_log_setup - atf_crash_log_addr : 0x0
[ATF][ 0.000000]mt_log_setup - atf_crash_log_size : 0x0
[ATF][ 0.000000]ATF log service is registered (0x7ffc0000, aee:0x7fffc000)
[ATF][ 0.000000]BL3-1: v1.0(debug):e7d64d4
[ATF][ 0.000000]BL3-1: Built : 10:50:39, Mar 21 2015
INFO: BL3-1: Initializing runtime services
[ATF][ 0.000000][BL31] Jump to FIQD for initialization！
INFO: BL3-1: Preparing for EL3 exit to normal world, LK
INFO: BL3-1: Next image address = 0x41e00000
INFO: BL3-1: Next image spsr = 0x1d3
[ATF][ 0.000000][BL31] Final dump！
[0] kernel_boot_opt=4
[0] 64Bit Kernel
[0] WDT NONRST=0x20000000
[0] [LEDS]LK: leds_init: mt65xx_backlight_off
[0] [LEDS]LK: mt65xx_backlight_off
[0] [LEDS]LK: LCD-backlight level is 0
[0] [pmic_init] LK Start..................
[0] [pmic_init] MT6325 CHIP Code = 0x2820
[0] [pmic_init] Done
[10] platform_init()
[20] [mmc_init]: msdc0 start mmc_init_host() in LK...
[20] [msdc_init]: msdc0 Host controller intialization start
[20] [MSDC] config VEMC to 3V in lk
[20] [SD0] Pins mode(1), none(0), down(1), up(2), keep(3)
[20] [SD0] Pins mode(2), none(0), down(1), up(2), keep(3)
[20] [MSDC] config VEMC to 3V in lk
[20] [info][msdc_set_startbit 1247] read data start bit at rising edge
[20] [info][msdc_config_clksrc] input clock is 400000kHz
[20] [SD0] Bus Width: 1
[20] [info][msdc_config_clksrc] input clock is 400000kHz
[20] [info][msdc_set_startbit 1247] read data start bit at rising edge
[20] [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) div(385) DS(0) RS(0)
[20] [msdc_init]: msdc0 Host controller intialization done
[20] [mmc_init]: msdc0 start mmc_init_card()in LK...
[20] [mmc_init_card]: start
[140] [info][msdc_config_clksrc] input clock is 400000kHz
[140] [info][msdc_set_startbit 1247] read data start bit at rising edge
[140] [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) div(385) DS(0) RS(0)
[140] [SD0] Bus Width: 8
[160] [SD0] Switch to High-Speed mode！
[160] [info][msdc_config_clksrc] input clock is 400000kHz
[160] [info][msdc_set_startbit 1247] read data start bit at rising edge
[160] [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(2) DDR(1) div(192) DS(0) RS(0)
[160] [SD0] Bus Width: 8
[160] [SD0] Size: 7456 MB, Max.Speed: 52000 kHz, blklen(512), nblks(15269888), ro(0)
[160] [mmc_init_mem_card 3240][SD0] Initialized, eMMC50
[160] before host->cur_bus_clk(259740)
[180] [info][msdc_config_clksrc] input clock is 400000kHz
[180] [info][msdc_set_startbit 1247] read data start bit at rising edge
[180] [SD0] SET_CLK(52000kHz): SCLK(50000kHz) MODE(2) DDR(1) div(1) DS(0) RS(0)
[180] host->cur_bus_clk(50000000)
[180] [mmc_init_card]: finish successfully
[180] [mt_part_register_device]
[180] [GPT_LK]Parsing Primary GPT now...
[180] [GPT_LK][0]name=proinfo, part_id=8, start_sect=0x400, nr_sects=0x1800
[180] [GPT_LK][1]name=nvram, part_id=8, start_sect=0x1c00, nr_sects=0x2800
[180] [GPT_LK][2]name=protect1, part_id=8, start_sect=0x4400, nr_sects=0x5000
[180] [GPT_LK][3]name=protect2, part_id=8, start_sect=0x9400, nr_sects=0x5000
[180] [GPT_LK][4]name=lk, part_id=8, start_sect=0xe400, nr_sects=0x400
[190] [GPT_LK][5]name=para, part_id=8, start_sect=0xe800, nr_sects=0x400
[200] [GPT_LK][6]name=boot, part_id=8, start_sect=0xec00, nr_sects=0x8000
[200] [GPT_LK][7]name=recovery, part_id=8, start_sect=0x16c00, nr_sects=0x8000
[200] [GPT_LK][8]name=logo, part_id=8, start_sect=0x1ec00, nr_sects=0x4000
[200] [GPT_LK][9]name=expdb, part_id=8, start_sect=0x22c00, nr_sects=0x5000
[200] [GPT_LK][10]name=seccfg, part_id=8, start_sect=0x27c00, nr_sects=0x400
[200] [GPT_LK][11]name=oemkeystore, part_id=8, start_sect=0x28000, nr_sects=0x1000
[200] [GPT_LK][12]name=secro, part_id=8, start_sect=0x29000, nr_sects=0x3000
[200] [GPT_LK][13]name=keystore, part_id=8, start_sect=0x2c000, nr_sects=0x4000
[200] [GPT_LK][14]name=tee1, part_id=8, start_sect=0x30000, nr_sects=0x2800
[200] [GPT_LK][15]name=tee2, part_id=8, start_sect=0x32800, nr_sects=0x2800
[200] [GPT_LK][16]name=frp, part_id=8, start_sect=0x35000, nr_sects=0x800
[210] [GPT_LK][17]name=nvdata, part_id=8, start_sect=0x35800, nr_sects=0x10000
[220] [GPT_LK][18]name=metadata, part_id=8, start_sect=0x45800, nr_sects=0x12800
[220] [GPT_LK][19]name=system, part_id=8, start_sect=0x58000, nr_sects=0x300000
[220] [GPT_LK][20]name=cache, part_id=8, start_sect=0x358000, nr_sects=0xc8000
[220] [GPT_LK][21]name=userdata, part_id=8, start_sect=0x420000, nr_sects=0xa67c00
[220] [GPT_LK][22]name=flashinfo, part_id=8, start_sect=0xe87c00, nr_sects=0x8000
[220] [GPT_LK]Success to find valid GPT.
[220] [SD0] boot device found
[220] [upmu_is_chr_det] 1
[220] [PART_LK][get_part] para
[LK_ENV]ENV initialize sucess
[LK_ENV]env:
off-mode-charge=1
data_free_size_th=52428800
[220] [DISP]func|disp_LCM_probe
[220] [DISP]func|_display_interface_path_init
[240] [DISPCHECK]dpmgr create path SUCCESS(0x41e4df38)
[240] [DISPCHECK]dpmgr set dst module FINISHED(dsi0 )
[240] [DISP]func|ddp_dsi_init
[240] [DISPCHECK]dsi0 init finished
[240] [DISP]func|ddp_dsi_config
[240] [DISPCHECK][DDPDSI] DSI Mode: SYNC_EVENT_VDO_MODE
[240] [DISPCHECK][DDPDSI] LANE_NUM: 4,data_format: 0,vertical_sync_active: 0
[240] [DISPCHECK][DDPDSI] vact: 10, vbp: 23, vfp: 12, vact_line: 600, hact: 10, hbp: 160, hfp: 160, hblank: 0, hblank: 1105566796
[240] [DISPCHECK][DDPDSI] pll_select: 0, pll_div1: 0, pll_div2: 0, fbk_div: 0,fbk_sel: 0, rg_bir: 0
[240] [DISPCHECK][DDPDSI] rg_bic: 0, rg_bp: 0, PLL_CLOCK: 175, dsi_clock: 0, ssc_range: 0, ssc_disable: 0, compatibility_for_nvk: 0, cont_clock: 0
[240] [DISPCHECK][DDPDSI] lcm_ext_te_enable: 0, noncont_clock: 0, noncont_clock_period: 0
[240] [DISP]func|DSI_PHY_clk_setting
[240] [DISP][mipitx/inreg]0x10206190=0x00000000
[260] [DISP][mipitx/reg]0x14017004=0x00000020
[260] [DISP][mipitx/reg]0x14017014=0x00000000
[260] [DISP][mipitx/reg]0x14017010=0x00000000
[260] [DISP][mipitx/reg]0x1401700c=0x00000000
[260] [DISP][mipitx/reg]0x14017008=0x00000000
[260] [DISP]PLL config: LNT=0x0,clk=0x20,lan3=0x20,lan2=0x0,lan1=0x0,lan0=0x0
[260] [DISP][mipitx/reg]0x14017044=0x88492481
[260] [DISP][mipitx/reg]0x14017044=0x88492483
[260] [DISP][mipitx/reg]0x14017040=0x00000082
[260] [DISP][mipitx/reg]0x14017000=0x00000402
[260] [DISP][mipitx/reg]0x14017000=0x00000403
[260] [DISP][mipitx/reg]0x14017068=0x00000003
[260] [DISP][mipitx/reg]0x14017068=0x00000101
[260] [DISP][mipitx/reg]0x14017050=0x00000008
[260] [DISP][mipitx/reg]0x14017050=0x00000008
[260] [DISP][mipitx/reg]0x14017050=0x00000008
[260] [DISP][mipitx/reg]0x14017054=0x00000003
[260] [DISP][mipitx/reg]0x14017058=0x35000000
[260] [DISP][mipitx/reg]0x14017058=0x35d80000
[280] [DISP][mipitx/reg]0x14017058=0x35d89d00
[280] [DISP][mipitx/reg]0x14017058=0x35d89d89
[280] [DISP][mipitx/reg]0x14017054=0x00000003
[280] [DISP][mipitx/reg]0x14017054=0x01b10003
[280] [DISP][mipitx/reg]0x1401705c=0x065d0000
[280] [DISP][mipitx/reg]0x1401705c=0x065d065d
[280] [DISP][dsi_drv.c] PLL config:data_rate=350,txdiv=2,pcw=903388553,delta1=5,pdelta1=0x65d
[280] [DISP][mipitx/reg]0x14017054=0x01b10007
[280] [DISP][mipitx/reg]0x14017004=0x00000021
[280] [DISP][mipitx/reg]0x14017008=0x00000001
[280] [DISP][mipitx/reg]0x1401700c=0x00000001
[280] [DISP][mipitx/reg]0x14017010=0x00000001
[280] [DISP][mipitx/reg]0x14017014=0x00000001
[280] [DISP][mipitx/reg]0x14017050=0x00000009
[280] [DISP][mipitx/reg]0x14017060=0x00000000
[280] [DISP][mipitx/reg]0x14017060=0x00000001
[280] [DISP][mipitx/reg]0x14017040=0x00000082
[280] DISP/[DISP] - kernel - DSI_PHY_TIMCONFIG, Cycle Time = 23(ns), Unit Interval = 3(ns). , lane# = 4
[300] DISP/[DISP] - kernel - DSI_PHY_TIMCONFIG, HS_TRAIL = 4, HS_ZERO = 7, HS_PRPR = 3, LPX = 3, TA_GET = 15, TA_SURE = 4, TA_GO = 12, CLK_TRAIL = 5,
[300] [DISP]func|_display_interface_path_deinit
[300] [DISPCHECK]dsi0 init finished
[300] [DISP][mipitx/reg]0x14017084=0x00000001
[300] [DISP][mipitx/reg]0x14017084=0x00000003
[300] [DISP][mipitx/reg]0x14017084=0x00000013
[300] [DISP][mipitx/reg]0x14017084=0x00000033
[300] [DISP][mipitx/reg]0x14017084=0x00000033
[300] [DISP][mipitx/reg]0x14017084=0x00000033
[300] [DISP][mipitx/reg]0x14017084=0x00000133
[300] [DISP][mipitx/reg]0x14017084=0x00000333
[300] [DISP][mipitx/reg]0x14017084=0x00010333
[300] [DISP][mipitx/reg]0x14017084=0x00020333
[300] [DISP][mipitx/reg]0x14017084=0x00100333
[300] [DISP][mipitx/reg]0x14017084=0x00200333
[300] [DISP][mipitx/reg]0x14017080=0x00000001
[320] [DISP][mipitx/reg]0x14017050=0x00000008
[320] [DISP][mipitx/reg]0x14017064=0x00000020
[320] [DISP][mipitx/reg]0x14017040=0x00000882
[320] [DISP][mipitx/reg]0x14017004=0x00000020
[320] [DISP][mipitx/reg]0x14017008=0x00000000
[320] [DISP][mipitx/reg]0x1401700c=0x00000000
[320] [DISP][mipitx/reg]0x14017010=0x00000000
[320] [DISP][mipitx/reg]0x14017014=0x00000000
[320] [DISP][mipitx/reg]0x14017068=0x00000103
[320] [DISP][mipitx/reg]0x14017068=0x00000102
[320] [DISP][mipitx/reg]0x14017040=0x00000880
[320] [DISP][mipitx/reg]0x14017000=0x00000401
[320] [DISP][mipitx/reg]0x14017000=0x00000400
[320] [DISP][mipitx/reg]0x14017044=0x88492481
[320] [DISP][mipitx/reg]0x14017044=0x88492480
[320] [DISP][mipitx/reg]0x14017050=0x00000008
[320] [DISP][mipitx/reg]0x14017050=0x00000000
[320] [DISP][mipitx/reg]0x14017050=0x00000000
[340] [DISP][mipitx/reg]0x14017050=0x00000000
[340] [DISP][mipitx/reg]0x14017054=0x00000000
[340] [DISP][mipitx/reg]0x14017058=0x50000000
[340] [DISP][mipitx/reg]0x14017080=0x00000000
[340] [DISPCHECK]******** dump lcm driver information ********
[340] [DISPCHECK][LCM], name: n711_ek79007_wsvga_dsi_vdo
[340] [DISPCHECK][LCM] resolution: 1024 x 600
[340] [DISPCHECK][LCM] physical size: 0 x 0
[340] [DISPCHECK][LCM] physical size: 0 x 0
[340] [DISPCHECK][LCM] lcm_if:0, cmd_if:0
[340] [DISPCHECK][LCM] interface: unknown
[340] [DISPCHECK][LCM] Type: DSI
[340] [DISPCHECK][LCM] DSI Mode: SYNC_EVENT_VDO_MODE
[340] [DISPCHECK][LCM] LANE_NUM: 4,data_format: 0,vertical_sync_active: 0
[340] [DISPCHECK][LCM] vact: 10, vbp: 23, vfp: 12, vact_line: 600, hact: 10, hbp: 160, hfp: 160, hblank: 0, hblank: 1105506872
[350] [DISPCHECK][LCM] pll_select: 0, pll_div1: 0, pll_div2: 0, fbk_div: 0,fbk_sel: 0, rg_bir: 0
[360] [DISPCHECK][LCM] rg_bic: 0, rg_bp: 0, PLL_CLOCK: 175, dsi_clock: 0, ssc_range: 0, ssc_disable: 0, compatibility_for_nvk: 0, cont_clock: 0
[360] [DISPCHECK][LCM] lcm_ext_te_enable: 0, noncont_clock: 0, noncont_clock_period: 0
[360] [DISP]lcm handle is null, after probe:0x41e4e494
[360] [DISP]^^ DISP_GetVRamSize: 8716288 bytes
[360] warning: size is not 2MB aligned
[360] mblock[0].start: 0x40000000, sz: 0x20000000, limit: 0x100000000, max_addr: 0x0, max_rank: 1, target: -1, mblock[].rank: 0
[360] mblock_reserve dbg[0]: 1, 1, 1, 1
[360] mblock[1].start: 0x60000000, sz: 0x1ffc0000, limit: 0x100000000, max_addr: 0x60000000, max_rank: 1, target: 0, mblock[].rank: 1
[360] mblock_reserve dbg[1]: 1, 1, 1, 1
[360] mblock_reserve: 7f770000 - 7ffc0000 from mblock 1
[360] FB base = 0x7f770000, FB size = 8716288
[370] fb_va: 0x7f770000, fb_pa: 0x7f770000, fb_pa_k: 0x7f770000
[380] [DISP]func|primary_display_init
[LK_ENV]get_env DFO
[380] [DISP]env buffer = <null>
[380] [DISP]env buffer = NULL
[380] [DISP]LCM_FAKE_WIDTH = [DEC]0 [HEX]0x00000000
[380] [DISP]LCM_FAKE_HEIGHT = [DEC]0 [HEX]0x00000000
[380] [DISP]LCM Resolution will be changed, original: 1024x600, now: 0x0
[380] [DISP]ERROR:Invalid resolution: 0x0
[380] [DISP]ERROR:[DISP_DFO]WARNING！ Change LCM Resolution FAILED！
[380] [DISPCHECK]disp_lcm_probe SUCCESS
[380] [DISP]func|disp_lcm_get_params
[380] [DISP]func|_build_path_direct_link
[380] [DISPCHECK]dpmgr create path SUCCESS(0x41e4df38)
[380] [DISPCHECK]dpmgr set dst module FINISHED(dsi0 )
[380] [DISPCHECK]primary display is DIRECT LINK MODE
[380] [DISPCHECK]primary display BUILD cmdq trigger loop finished
[380] [DISPCHECK]primary display START cmdq trigger loop finished
[380] [DISP]func|disp_lcm_is_video_mode
[400] [DISP]func|ddp_dsi_init
[400] [DISPCHECK]dsi0 init finished
[400] [DISP]func|ddp_dsi_config
[400] [DISPCHECK][DDPDSI] DSI Mode: SYNC_EVENT_VDO_MODE
[400] [DISPCHECK][DDPDSI] LANE_NUM: 4,data_format: 0,vertical_sync_active: 0
[400] [DISPCHECK][DDPDSI] vact: 10, vbp: 23, vfp: 12, vact_line: 600, hact: 10, hbp: 160, hfp: 160, hblank: 0, hblank: 1105566796
[400] [DISPCHECK][DDPDSI] pll_select: 0, pll_div1: 0, pll_div2: 0, fbk_div: 0,fbk_sel: 0, rg_bir: 0
[400] [DISPCHECK][DDPDSI] rg_bic: 0, rg_bp: 0, PLL_CLOCK: 175, dsi_clock: 0, ssc_range: 0, ssc_disable: 0, compatibility_for_nvk: 0, cont_clock: 0
[400] [DISPCHECK][DDPDSI] lcm_ext_te_enable: 0, noncont_clock: 0, noncont_clock_period: 0
[400] [DISP]func|DSI_PHY_clk_setting
[400] [DISP][mipitx/inreg]0x10206190=0x00000000
[400] [DISP][mipitx/reg]0x14017004=0x00000020
[400] [DISP][mipitx/reg]0x14017014=0x00000000
[400] [DISP][mipitx/reg]0x14017010=0x00000000
[420] [DISP][mipitx/reg]0x1401700c=0x00000000
[420] [DISP][mipitx/reg]0x14017008=0x00000000
[420] [DISP]PLL config: LNT=0x0,clk=0x20,lan3=0x20,lan2=0x0,lan1=0x0,lan0=0x0
[420] [DISP][mipitx/reg]0x14017044=0x88492481
[420] [DISP][mipitx/reg]0x14017044=0x88492483
[420] [DISP][mipitx/reg]0x14017040=0x00000882
[420] [DISP][mipitx/reg]0x14017000=0x00000402
[420] [DISP][mipitx/reg]0x14017000=0x00000403
[420] [DISP][mipitx/reg]0x14017068=0x00000003
[420] [DISP][mipitx/reg]0x14017068=0x00000101
[420] [DISP][mipitx/reg]0x14017050=0x00000008
[420] [DISP][mipitx/reg]0x14017050=0x00000008
[420] [DISP][mipitx/reg]0x14017050=0x00000008
[420] [DISP][mipitx/reg]0x14017054=0x00000001
[420] [DISP][mipitx/reg]0x14017058=0x35000000
[420] [DISP][mipitx/reg]0x14017058=0x35d80000
[420] [DISP][mipitx/reg]0x14017058=0x35d89d00
[420] [DISP][mipitx/reg]0x14017058=0x35d89d89
[420] [DISP][mipitx/reg]0x14017054=0x00000003
[440] [DISP][mipitx/reg]0x14017054=0x01b10003
[440] [DISP][mipitx/reg]0x1401705c=0x065d065d
[440] [DISP][mipitx/reg]0x1401705c=0x065d065d
[440] [DISP][dsi_drv.c] PLL config:data_rate=350,txdiv=2,pcw=903388553,delta1=5,pdelta1=0x65d
[440] [DISP][mipitx/reg]0x14017054=0x01b10007
[440] [DISP][mipitx/reg]0x14017004=0x00000021
[440] [DISP][mipitx/reg]0x14017008=0x00000001
[440] [DISP][mipitx/reg]0x1401700c=0x00000001
[440] [DISP][mipitx/reg]0x14017010=0x00000001
[440] [DISP][mipitx/reg]0x14017014=0x00000001
[440] [DISP][mipitx/reg]0x14017050=0x00000009
[440] [DISP][mipitx/reg]0x14017060=0x00000000
[440] [DISP][mipitx/reg]0x14017060=0x00000001
[440] [DISP][mipitx/reg]0x14017040=0x00000082
[440] DISP/[DISP] - kernel - DSI_PHY_TIMCONFIG, Cycle Time = 23(ns), Unit Interval = 3(ns). , lane# = 4
[440] DISP/[DISP] - kernel - DSI_PHY_TIMCONFIG, HS_TRAIL = 4, HS_ZERO = 7, HS_PRPR = 3, LPX = 3, TA_GET = 15, TA_SURE = 4, TA_GO = 12, CLK_TRAIL = 5,
[460] [DISP]func|disp_lcm_init
===================== lcm_gpio_set 152: num:78 => 1 =======================
===================== lcm_gpio_set 152: num:147 => 1 =======================
[IND][K] y_____0init_lcm_registers
[740] [DISP]func|DSI_set_cmdq
[740] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[740] [DISP]func|DSI_set_cmdq
[740] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[740] [DISP]func|DSI_set_cmdq
[740] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[740] [DISP]func|DSI_set_cmdq
[740] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[740] [DISP]func|DSI_set_cmdq
[740] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[760] [DISP]func|DSI_set_cmdq
[760] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[760] [DISP]func|DSI_set_cmdq
[760] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[860] [DISP]func|DSI_dcs_read_lcm_reg_v2
[860] DISP/ Start polling DSI read ready！
[860] DISP/ End polling DSI read ready！
[860] [DISP]DSI_CMDQ_SIZE : 0x1
[860] [DISP]DSI_CMDQ_DATA0 : 0x4
[860] [DISP]DSI_CMDQ_DATA1 : 0x6
[860] [DISP]DSI_CMDQ_DATA2 : 0xa
[860] [DISP]DSI_CMDQ_DATA3 : 0x0
[860] [DISP]DSI_RX_DATA0 : 0x12000021
[860] [DISP]DSI_RX_DATA1 : 0x10f0f08
[860] [DISP]DSI_RX_DATA2 : 0x0
[860] [DISP]DSI_RX_DATA3 : 0x0
[860] [DISP]read_data0, 21,0,0,12
[860] [DISP]read_data1, 8,f,f,1
[880] [DISP]read_data2, 0,0,0,0
[880] [DISP]read_data3, 0,0,0,0
[880] DISP/ DSI read packet_type is 0x21
[880] [DISP]lcm is connected
[880] [DISP]func|disp_lcm_is_video_mode
[880] [DISP]func|primary_display_config_input
[880] [DISP]func|ddp_dsi_is_busy
[880] [DISP]func|ddp_dsi_config
[880] [DISP]func|primary_display_config_input
[880] [DISP]func|ddp_dsi_is_busy
[880] [DISP]func|ddp_dsi_config
[880] mt_get_logo_db_addr: 0x7f370000
[920] fb dump: 0x00000000, 0x00000000, 0x00000000, 0x00000000
[940] [DISP]func|primary_display_trigger
[940] [DISP]func|ddp_dsi_is_busy
[940] [DISPCHECK]trigger mode: DIRECT_LINK
[940] [DISP]func|disp_lcm_is_video_mode
[940] [DISP]func|disp_lcm_is_video_mode
[940] s_mt65xx_gd.gdfIndex=3[940] mt_get_logo_db_addr_pa: 0x7f370000
[940] [PART_LK][get_part] logo
[940] [PART_LK][get_part] logo
=========================================
[940] [LK_BOOT] logo magic number : 0x58881688
[940] [LK_BOOT] logo name : LOGO
[940] [LK_BOOT] logo size : 802341
=========================================
read the data of logo
kedump mini start
kedump: boot_reason(1)
RAM_CONSOLE. sram(0x12c000) sig 0 mismatch
RAM_CONSOLE. start: 0x43f00000, size: 0x10000
RAM_CONSOLE. lk size mismatch 0 + c0 ！= 100
[980] D:No boot record found at 0x41f00000[0000]
[980] detecting pmic just reset
[mboot_recovery_load_misc]: size is 6144
[mboot_recovery_load_misc]: misc_addr is 0x41e6d548
[980] [PART_LK][get_part] para
[980] [LK_BOOT] Load '<null>' partition to 0x41E6D548 (6144 bytes in 2 ms)
[980] MT65XX_FACTORY_KEY 0x0
[980] MT65XX_BOOT_MENU_KEY 0x11
[980] MT65XX_RECOVERY_KEY 0x11
[980] mtk detect key function key = 0
[980] mtk detect key function key = 17
[980] mtk detect key function key = 17
[980] mtk detect key function key = 0
[980] mtk detect key function key = 17
[980] mtk detect key function key = 17
[980] mtk detect key function key = 0
[980] mtk detect key function key = 17
[980] mtk detect key function key = 17
[1000] mtk detect key function key = 0
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 0
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 0
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 0
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 0
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 0
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 0
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 17
[1000] mtk detect key function key = 0
[1010] mtk detect key function key = 17
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 0
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 0
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 0
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 0
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 0
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 0
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 0
[1020] mtk detect key function key = 17
[1020] mtk detect key function key = 17
[1040] mtk detect key function key = 0
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 0
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 0
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 0
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 0
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 0
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 0
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 17
[1040] mtk detect key function key = 0
[1040] mtk detect key function key = 17
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 0
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 0
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 0
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 0
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 0
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 0
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 0
[1060] mtk detect key function key = 17
[1060] mtk detect key function key = 17
[1070] mtk detect key function key = 0
[1080] mtk detect key function key = 17
[1080] mtk detect key function key = 17
[1080] mtk detect key function key = 0
[1080] mtk detect key function key = 17
[1080] mtk detect key function key = 17
[1080] mtk detect key function key = 0
[1080] mtk detect key function key = 17
[1080] mtk detect key function key = 17
[1080] mtk detect key function key = 0
[1080] mtk detect key function key = 17
[1080] mtk detect key function key = 17
[LK_ENV]get_env off-mode-charge
[1080] [upmu_is_chr_det] 1
< Kernel Power Off Charging Detection Ok>
[1080] [AUXADC] ch=0 raw=24501 data=4037
[1080] [mt65xx_bat_init] check VBAT=4037 mV with 3450 mV
[1080] [upmu_is_chr_det] 1
[1080] mt_get_logo_db_addr: 0x7f370000
[1080] mt_get_tempfb_addr: 0x7fc30000
[1180] fb dump: 0x00000000, 0xff000000, 0xff000000, 0xff0000