大家有没有遇到 5.0寸屏驱动IC otm8018b在开机后不久就白屏，然后自动重启的现象？
时间：10-02
整理：3721RD
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RGB接口，以下是代码#include "LCD.h"
#include "delay.h"
#define SPI_WriteComm LCD_WR_REG_SPI
#define SPI_WriteData LCD_WR_DATA_SPI
#define Delay delay_ms
void LCM_Initcode(void)
{
LCD_SPI_Reset();
/*
//ivo463
SPI_WriteComm(0xFF00); SPI_WriteData(0x80);
SPI_WriteComm(0xFF01); SPI_WriteData(0x09);
SPI_WriteComm(0xFF02); SPI_WriteData(0x01);
SPI_WriteComm(0xFF80); SPI_WriteData(0x80);
SPI_WriteComm(0xFF81); SPI_WriteData(0x09);
SPI_WriteComm(0xC0B4); SPI_WriteData(0x50);
SPI_WriteComm(0xC582); SPI_WriteData(0xA3);
SPI_WriteComm(0xC590); SPI_WriteData(0x96);
SPI_WriteComm(0xC591); SPI_WriteData(0x87);
SPI_WriteComm(0xD800); SPI_WriteData(0x87);
SPI_WriteComm(0xD801); SPI_WriteData(0x87);
SPI_WriteComm(0xD900); SPI_WriteData(0x4E);
SPI_WriteComm(0xC181); SPI_WriteData(0x66);
SPI_WriteComm(0xC1A0); SPI_WriteData(0xEA);
SPI_WriteComm(0xC1A1); SPI_WriteData(0x08);
SPI_WriteComm(0xC489); SPI_WriteData(0x08);
SPI_WriteComm(0xC0A3); SPI_WriteData(0x00);
SPI_WriteComm(0xC481); SPI_WriteData(0x83);
SPI_WriteComm(0xC592); SPI_WriteData(0x01);
SPI_WriteComm(0xC5B1); SPI_WriteData(0xA9);
SPI_WriteComm(0xCFC7); SPI_WriteData(0x02);
SPI_WriteComm(0xB390); SPI_WriteData(0x02);
SPI_WriteComm(0xB392); SPI_WriteData(0x45);
SPI_WriteComm(0xC080); SPI_WriteData(0x00);
SPI_WriteComm(0xC081); SPI_WriteData(0x58);
SPI_WriteComm(0xC082); SPI_WriteData(0x00);
SPI_WriteComm(0xC083); SPI_WriteData(0x15);
SPI_WriteComm(0xC084); SPI_WriteData(0x15);
SPI_WriteComm(0xC085); SPI_WriteData(0x00);
SPI_WriteComm(0xC086); SPI_WriteData(0x58);
SPI_WriteComm(0xC087); SPI_WriteData(0x15);
SPI_WriteComm(0xC088); SPI_WriteData(0x15);
SPI_WriteComm(0xC090); SPI_WriteData(0x00);
SPI_WriteComm(0xC091); SPI_WriteData(0x44);
SPI_WriteComm(0xC092); SPI_WriteData(0x00);
SPI_WriteComm(0xC093); SPI_WriteData(0x00);
SPI_WriteComm(0xC094); SPI_WriteData(0x00);
SPI_WriteComm(0xC095); SPI_WriteData(0x03);
SPI_WriteComm(0xC1A6); SPI_WriteData(0x01);
SPI_WriteComm(0xC1A7); SPI_WriteData(0x00);
SPI_WriteComm(0xC1A8); SPI_WriteData(0x00);
SPI_WriteComm(0xCE80); SPI_WriteData(0x87);
SPI_WriteComm(0xCE81); SPI_WriteData(0x03);
SPI_WriteComm(0xCE82); SPI_WriteData(0x00);
SPI_WriteComm(0xCE83); SPI_WriteData(0x86);
SPI_WriteComm(0xCE84); SPI_WriteData(0x03);
SPI_WriteComm(0xCE85); SPI_WriteData(0x00);
SPI_WriteComm(0xCE86); SPI_WriteData(0x85);
SPI_WriteComm(0xCE87); SPI_WriteData(0x03);
SPI_WriteComm(0xCE88); SPI_WriteData(0x00);
SPI_WriteComm(0xCE89); SPI_WriteData(0x84);
SPI_WriteComm(0xCE8A); SPI_WriteData(0x03);
SPI_WriteComm(0xCE8B); SPI_WriteData(0x00);
SPI_WriteComm(0xCE90); SPI_WriteData(0x33);
SPI_WriteComm(0xCE91); SPI_WriteData(0x52);
SPI_WriteComm(0xCE92); SPI_WriteData(0x00);
SPI_WriteComm(0xCE93); SPI_WriteData(0x33);
SPI_WriteComm(0xCE94); SPI_WriteData(0x53);
SPI_WriteComm(0xCE95); SPI_WriteData(0x00);
SPI_WriteComm(0xCE96); SPI_WriteData(0x33);
SPI_WriteComm(0xCE97); SPI_WriteData(0x54);
SPI_WriteComm(0xCE98); SPI_WriteData(0x00);
SPI_WriteComm(0xCE99); SPI_WriteData(0x33);
SPI_WriteComm(0xCE9A); SPI_WriteData(0x55);
SPI_WriteComm(0xCE9B); SPI_WriteData(0x00);
SPI_WriteComm(0xCE9C); SPI_WriteData(0x00);
SPI_WriteComm(0xCE9D); SPI_WriteData(0x00);
SPI_WriteComm(0xCEA0); SPI_WriteData(0x38);
SPI_WriteComm(0xCEA1); SPI_WriteData(0x05);
SPI_WriteComm(0xCEA2); SPI_WriteData(0x03);
SPI_WriteComm(0xCEA3); SPI_WriteData(0x56);
SPI_WriteComm(0xCEA4); SPI_WriteData(0x00);
SPI_WriteComm(0xCEA5); SPI_WriteData(0x00);
SPI_WriteComm(0xCEA6); SPI_WriteData(0x00);
SPI_WriteComm(0xCEA7); SPI_WriteData(0x38);
SPI_WriteComm(0xCEA8); SPI_WriteData(0x04);
SPI_WriteComm(0xCEA9); SPI_WriteData(0x03);
SPI_WriteComm(0xCEAA); SPI_WriteData(0x57);
SPI_WriteComm(0xCEAB); SPI_WriteData(0x00);
SPI_WriteComm(0xCEAC); SPI_WriteData(0x00);
SPI_WriteComm(0xCEAD); SPI_WriteData(0x00);
SPI_WriteComm(0xCEB0); SPI_WriteData(0x38);
SPI_WriteComm(0xCEB1); SPI_WriteData(0x03);
SPI_WriteComm(0xCEB2); SPI_WriteData(0x03);
SPI_WriteComm(0xCEB3); SPI_WriteData(0x58);
SPI_WriteComm(0xCEB4); SPI_WriteData(0x00);
SPI_WriteComm(0xCEB5); SPI_WriteData(0x00);
SPI_WriteComm(0xCEB6); SPI_WriteData(0x00);
SPI_WriteComm(0xCEB7); SPI_WriteData(0x38);
SPI_WriteComm(0xCEB8); SPI_WriteData(0x02);
SPI_WriteComm(0xCEB9); SPI_WriteData(0x03);
SPI_WriteComm(0xCEBA); SPI_WriteData(0x59);
SPI_WriteComm(0xCEBB); SPI_WriteData(0x00);
SPI_WriteComm(0xCEBC); SPI_WriteData(0x00);
SPI_WriteComm(0xCEBD); SPI_WriteData(0x00);
SPI_WriteComm(0xCEC0); SPI_WriteData(0x38);
SPI_WriteComm(0xCEC1); SPI_WriteData(0x01);
SPI_WriteComm(0xCEC2); SPI_WriteData(0x03);
SPI_WriteComm(0xCEC3); SPI_WriteData(0x5A);
SPI_WriteComm(0xCEC4); SPI_WriteData(0x00);
SPI_WriteComm(0xCEC5); SPI_WriteData(0x00);
SPI_WriteComm(0xCEC6); SPI_WriteData(0x00);
SPI_WriteComm(0xCEC7); SPI_WriteData(0x38);
SPI_WriteComm(0xCEC8); SPI_WriteData(0x00);
SPI_WriteComm(0xCEC9); SPI_WriteData(0x03);
SPI_WriteComm(0xCECA); SPI_WriteData(0x5C);
SPI_WriteComm(0xCECB); SPI_WriteData(0x00);
SPI_WriteComm(0xCECC); SPI_WriteData(0x00);
SPI_WriteComm(0xCECD); SPI_WriteData(0x00);
SPI_WriteComm(0xCED0); SPI_WriteData(0X30);
SPI_WriteComm(0xCED1); SPI_WriteData(0x00);
SPI_WriteComm(0xCED2); SPI_WriteData(0x03);
SPI_WriteComm(0xCED3); SPI_WriteData(0x5C);
SPI_WriteComm(0xCED4); SPI_WriteData(0x00);
SPI_WriteComm(0xCED5); SPI_WriteData(0x00);
SPI_WriteComm(0xCED6); SPI_WriteData(0x00);
SPI_WriteComm(0xCED7); SPI_WriteData(0x30);
SPI_WriteComm(0xCED8); SPI_WriteData(0x01);
SPI_WriteComm(0xCED9); SPI_WriteData(0x03);
SPI_WriteComm(0xCEDA); SPI_WriteData(0x5D);
SPI_WriteComm(0xCEDB); SPI_WriteData(0x00);
SPI_WriteComm(0xCEDC); SPI_WriteData(0x00);
SPI_WriteComm(0xCEDD); SPI_WriteData(0x00);
SPI_WriteComm(0xCBC3); SPI_WriteData(0x04);
SPI_WriteComm(0xCBC4); SPI_WriteData(0x04);
SPI_WriteComm(0xCBC5); SPI_WriteData(0x04);
SPI_WriteComm(0xCBC6); SPI_WriteData(0x04);
SPI_WriteComm(0xCBC7); SPI_WriteData(0x04);
SPI_WriteComm(0xCBC8); SPI_WriteData(0x04);
SPI_WriteComm(0xCBC9); SPI_WriteData(0x04);
SPI_WriteComm(0xCBCA); SPI_WriteData(0x04);
SPI_WriteComm(0xCBD8); SPI_WriteData(0x04);
SPI_WriteComm(0xCBD9); SPI_WriteData(0x04);
SPI_WriteComm(0xCBDA); SPI_WriteData(0x04);
SPI_WriteComm(0xCBDB); SPI_WriteData(0x04);
SPI_WriteComm(0xCBDC); SPI_WriteData(0x04);
SPI_WriteComm(0xCBDD); SPI_WriteData(0x04);
SPI_WriteComm(0xCBDE); SPI_WriteData(0x04);
SPI_WriteComm(0xCBE0); SPI_WriteData(0x04);
SPI_WriteComm(0xCC83); SPI_WriteData(0x03);
SPI_WriteComm(0xCC84); SPI_WriteData(0x01);
SPI_WriteComm(0xCC85); SPI_WriteData(0x09);
SPI_WriteComm(0xCC86); SPI_WriteData(0x0B);
SPI_WriteComm(0xCC87); SPI_WriteData(0x0D);
SPI_WriteComm(0xCC88); SPI_WriteData(0x0F);
SPI_WriteComm(0xCC89); SPI_WriteData(0x05);
SPI_WriteComm(0xCC90); SPI_WriteData(0x07);
SPI_WriteComm(0xCC9D); SPI_WriteData(0x04);
SPI_WriteComm(0xCC9E); SPI_WriteData(0x02);
SPI_WriteComm(0xCCA0); SPI_WriteData(0x0A);
SPI_WriteComm(0xCCA1); SPI_WriteData(0x0C);
SPI_WriteComm(0xCCA2); SPI_WriteData(0x0E);
SPI_WriteComm(0xCCA3); SPI_WriteData(0x10);
SPI_WriteComm(0xCCA4); SPI_WriteData(0x06);
SPI_WriteComm(0xCCA5); SPI_WriteData(0x08);
SPI_WriteComm(0xCCB3); SPI_WriteData(0x06);
SPI_WriteComm(0xCCB4); SPI_WriteData(0x08);
SPI_WriteComm(0xCCB5); SPI_WriteData(0x0A);
SPI_WriteComm(0xCCB6); SPI_WriteData(0x10);
SPI_WriteComm(0xCCB7); SPI_WriteData(0x0E);
SPI_WriteComm(0xCCB8); SPI_WriteData(0x0C);
SPI_WriteComm(0xCCB9); SPI_WriteData(0x04);
SPI_WriteComm(0xCCC0); SPI_WriteData(0x02);
SPI_WriteComm(0xCCCD); SPI_WriteData(0x05);
SPI_WriteComm(0xCCCE); SPI_WriteData(0x07);
SPI_WriteComm(0xCCD0); SPI_WriteData(0x09);
SPI_WriteComm(0xCCD1); SPI_WriteData(0x0F);
SPI_WriteComm(0xCCD2); SPI_WriteData(0x0D);
SPI_WriteComm(0xCCD3); SPI_WriteData(0x0B);
SPI_WriteComm(0xCCD4); SPI_WriteData(0x03);
SPI_WriteComm(0xCCD5); SPI_WriteData(0x01);
SPI_WriteComm(0xE100); SPI_WriteData(0x04);
SPI_WriteComm(0xE101); SPI_WriteData(0x0D);
SPI_WriteComm(0xE102); SPI_WriteData(0x12);
SPI_WriteComm(0xE103); SPI_WriteData(0x0F);
SPI_WriteComm(0xE104); SPI_WriteData(0x09);
SPI_WriteComm(0xE105); SPI_WriteData(0x1C);
SPI_WriteComm(0xE106); SPI_WriteData(0x0E);
SPI_WriteComm(0xE107); SPI_WriteData(0x0E);
SPI_WriteComm(0xE108); SPI_WriteData(0x00);
SPI_WriteComm(0xE109); SPI_WriteData(0x05);
SPI_WriteComm(0xE10A); SPI_WriteData(0x02);
SPI_WriteComm(0xE10B); SPI_WriteData(0x06);
SPI_WriteComm(0xE10C); SPI_WriteData(0x0E);
SPI_WriteComm(0xE10D); SPI_WriteData(0x1D);
SPI_WriteComm(0xE10E); SPI_WriteData(0x1A);
SPI_WriteComm(0xE10F); SPI_WriteData(0x12);
SPI_WriteComm(0xE200); SPI_WriteData(0x04);
SPI_WriteComm(0xE201); SPI_WriteData(0x0D);
SPI_WriteComm(0xE202); SPI_WriteData(0x12);
SPI_WriteComm(0xE203); SPI_WriteData(0x0E);
SPI_WriteComm(0xE204); SPI_WriteData(0x08);
SPI_WriteComm(0xE205); SPI_WriteData(0x1C);
SPI_WriteComm(0xE206); SPI_WriteData(0x0E);
SPI_WriteComm(0xE207); SPI_WriteData(0x0E);
SPI_WriteComm(0xE208); SPI_WriteData(0x00);
SPI_WriteComm(0xE209); SPI_WriteData(0x04);
SPI_WriteComm(0xE20A); SPI_WriteData(0x03);
SPI_WriteComm(0xE20B); SPI_WriteData(0x07);
SPI_WriteComm(0xE20C); SPI_WriteData(0x0E);
SPI_WriteComm(0xE20D); SPI_WriteData(0x1E);
SPI_WriteComm(0xE20E); SPI_WriteData(0x1B);
SPI_WriteComm(0xE20F); SPI_WriteData(0x12);
SPI_WriteComm(0xFF00); SPI_WriteData(0xFF);
SPI_WriteComm(0xFF01); SPI_WriteData(0xFF);
SPI_WriteComm(0xFF02); SPI_WriteData(0xFF);
SPI_WriteComm(0x3A00); SPI_WriteData(0x77);
SPI_WriteComm(0x1100);
Delay(120);
SPI_WriteComm(0x2900);
*/
//hsd4.3
SPI_WriteComm(0xff00); //
SPI_WriteData(0x80);
SPI_WriteComm(0xff01); // enable EXTC
SPI_WriteData(0x09);
SPI_WriteComm(0xff02); //
SPI_WriteData(0x01);
SPI_WriteComm(0xff80); // enable Orise mode
SPI_WriteData(0x80);
SPI_WriteComm(0xff81); //
SPI_WriteData(0x09);
SPI_WriteComm(0xff03); // enable SPI+I2C cmd2 read
SPI_WriteData(0x01);
//gamma DC
SPI_WriteComm(0xc0b4); //1+2dot inversion
SPI_WriteData(0x10);
SPI_WriteComm(0xC489); //reg off
SPI_WriteData(0x08);
SPI_WriteComm(0xC0a3); //pre-charge //V02
SPI_WriteData(0x00);
SPI_WriteComm(0xC582); //REG-pump23
SPI_WriteData(0xA3);
SPI_WriteComm(0xC590); //Pump setting (3x=D6)-->(2x=96)//v02 01/11
SPI_WriteData(0xd6);
SPI_WriteComm(0xC591); //Pump setting(VGH/VGL)
SPI_WriteData(0x87);
SPI_WriteComm(0xD800); //GVDD=4.5V
SPI_WriteData(0x74);
SPI_WriteComm(0xD801); //NGVDD=4.5V
SPI_WriteData(0x72);
//VCOMDC
SPI_WriteComm(0xd900); // VCOMDC=
SPI_WriteData(0x60);
SPI_WriteComm(0xE100); SPI_WriteData(0x09);
SPI_WriteComm(0xE101); SPI_WriteData(0x0a);
SPI_WriteComm(0xE102); SPI_WriteData(0x0e);
SPI_WriteComm(0xE103); SPI_WriteData(0x0d);
SPI_WriteComm(0xE104); SPI_WriteData(0x07);
SPI_WriteComm(0xE105); SPI_WriteData(0x18);
SPI_WriteComm(0xE106); SPI_WriteData(0x0d);
SPI_WriteComm(0xE107); SPI_WriteData(0x0d);
SPI_WriteComm(0xE108); SPI_WriteData(0x01);
SPI_WriteComm(0xE109); SPI_WriteData(0x04);
SPI_WriteComm(0xE10A); SPI_WriteData(0x05);
SPI_WriteComm(0xE10B); SPI_WriteData(0x06);
SPI_WriteComm(0xE10C); SPI_WriteData(0x0e);
SPI_WriteComm(0xE10D); SPI_WriteData(0x25);
SPI_WriteComm(0xE10E); SPI_WriteData(0x22);
SPI_WriteComm(0xE10F); SPI_WriteData(0x05);
// Negative
SPI_WriteComm(0xE200); SPI_WriteData(0x09);
SPI_WriteComm(0xE201); SPI_WriteData(0x0a);
SPI_WriteComm(0xE202); SPI_WriteData(0x0e);
SPI_WriteComm(0xE203); SPI_WriteData(0x0d);
SPI_WriteComm(0xE204); SPI_WriteData(0x07);
SPI_WriteComm(0xE205); SPI_WriteData(0x18);
SPI_WriteComm(0xE206); SPI_WriteData(0x0d);
SPI_WriteComm(0xE207); SPI_WriteData(0x0d);
SPI_WriteComm(0xE208); SPI_WriteData(0x01);
SPI_WriteComm(0xE209); SPI_WriteData(0x04);
SPI_WriteComm(0xE20A); SPI_WriteData(0x05);
SPI_WriteComm(0xE20B); SPI_WriteData(0x06);
SPI_WriteComm(0xE20C); SPI_WriteData(0x0e);
SPI_WriteComm(0xE20D); SPI_WriteData(0x25);
SPI_WriteComm(0xE20E); SPI_WriteData(0x22);
SPI_WriteComm(0xE20F); SPI_WriteData(0x05);
SPI_WriteComm(0xC181); //Frame rate 65Hz//V02
SPI_WriteData(0x66);
// RGB I/F setting VSYNC for OTM8018 0x0e
SPI_WriteComm(0xC1a1); //external Vsync(08) /Vsync,Hsync(0c) /Vsync,Hsync,DE(0e) //V02(0e) / all included clk(0f)
SPI_WriteData(0x08);
//SPI_WriteComm(0xC0a3); //pre-charge //V02
//SPI_WriteData(0x1b);
SPI_WriteComm(0xC481); //source bias //V02
SPI_WriteData(0x83);
SPI_WriteComm(0xC592); //Pump45
SPI_WriteData(0x01);//(01)
SPI_WriteComm(0xC5B1); //DC voltage setting ;[0]GVDD output, default: 0xa8
SPI_WriteData(0xA9);
SPI_WriteComm(0xC480); //no-display Source output = GND
SPI_WriteData(0x30);
//--------------------------------------------------------------------------------
// initial setting 2 < tcon_goa_wave >
//--------------------------------------------------------------------------------
// CE8x : vst1, vst2, vst3, vst4
SPI_WriteComm(0xCE80); // ce81[7:0] : vst1_shift[7:0]
SPI_WriteData(0x85);
SPI_WriteComm(0xCE81); // ce82[7:0] : 0000, vst1_width[3:0]
SPI_WriteData(0x03);
SPI_WriteComm(0xCE82); // ce83[7:0] : vst1_tchop[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCE83); // ce84[7:0] : vst2_shift[7:0]
SPI_WriteData(0x84);
SPI_WriteComm(0xCE84); // ce85[7:0] : 0000, vst2_width[3:0]
SPI_WriteData(0x03);
SPI_WriteComm(0xCE85); // ce86[7:0] : vst2_tchop[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCE86); // ce87[7:0] : vst3_shift[7:0]
SPI_WriteData(0x83);
SPI_WriteComm(0xCE87); // ce88[7:0] : 0000, vst3_width[3:0]
SPI_WriteData(0x03);
SPI_WriteComm(0xCE88); // ce89[7:0] : vst3_tchop[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCE89); // ce8a[7:0] : vst4_shift[7:0]
SPI_WriteData(0x82);
SPI_WriteComm(0xCE8a); // ce8b[7:0] : 0000, vst4_width[3:0]
SPI_WriteData(0x03);
SPI_WriteComm(0xCE8b); // ce8c[7:0] : vst4_tchop[7:0]
SPI_WriteData(0x00);
//CEAx : clka1, clka2
SPI_WriteComm(0xCEa0); // cea1[7:0] : clka1_width[3:0], clka1_shift[11:8]
SPI_WriteData(0x38);
SPI_WriteComm(0xCEa1); // cea2[7:0] : clka1_shift[7:0]
SPI_WriteData(0x02);
SPI_WriteComm(0xCEa2); // cea3[7:0] : clka1_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]
SPI_WriteData(0x03);
SPI_WriteComm(0xCEa3); // cea4[7:0] : clka1_switch[7:0]
SPI_WriteData(0x21);
SPI_WriteComm(0xCEa4); // cea5[7:0] : clka1_extend[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEa5); // cea6[7:0] : clka1_tchop[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEa6); // cea7[7:0] : clka1_tglue[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEa7); // cea8[7:0] : clka2_width[3:0], clka2_shift[11:8]
SPI_WriteData(0x38);
SPI_WriteComm(0xCEa8); // cea9[7:0] : clka2_shift[7:0]
SPI_WriteData(0x01);
SPI_WriteComm(0xCEa9); // ceaa[7:0] : clka2_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]
SPI_WriteData(0x03);
SPI_WriteComm(0xCEaa); // ceab[7:0] : clka2_switch[7:0]
SPI_WriteData(0x22);
SPI_WriteComm(0xCEab); // ceac[7:0] : clka2_extend
SPI_WriteData(0x00);
SPI_WriteComm(0xCEac); // cead[7:0] : clka2_tchop
SPI_WriteData(0x00);
SPI_WriteComm(0xCEad); // ceae[7:0] : clka2_tglue
SPI_WriteData(0x00);
//CEBx : clka3, clka4
SPI_WriteComm(0xCEb0); // ceb1[7:0] : clka3_width[3:0], clka3_shift[11:8]
SPI_WriteData(0x38);
SPI_WriteComm(0xCEb1); // ceb2[7:0] : clka3_shift[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEb2); // ceb3[7:0] : clka3_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]
SPI_WriteData(0x03);
SPI_WriteComm(0xCEb3); // ceb4[7:0] : clka3_switch[7:0]
SPI_WriteData(0x23);
SPI_WriteComm(0xCEb4); // ceb5[7:0] : clka3_extend[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEb5); // ceb6[7:0] : clka3_tchop[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEb6); // ceb7[7:0] : clka3_tglue[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEb7); // ceb8[7:0] : clka4_width[3:0], clka2_shift[11:8]
SPI_WriteData(0x30);
SPI_WriteComm(0xCEb8); // ceb9[7:0] : clka4_shift[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEb9); // ceba[7:0] : clka4_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]
SPI_WriteData(0x03);
SPI_WriteComm(0xCEba); // cebb[7:0] : clka4_switch[7:0]
SPI_WriteData(0x24);
SPI_WriteComm(0xCEbb); // cebc[7:0] : clka4_extend
SPI_WriteData(0x00);
SPI_WriteComm(0xCEbc); // cebd[7:0] : clka4_tchop
SPI_WriteData(0x00);
SPI_WriteComm(0xCEbd); // cebe[7:0] : clka4_tglue
SPI_WriteData(0x00);
//CECx : clkb1, clkb2
SPI_WriteComm(0xCEc0); // cec1[7:0] : clkb1_width[3:0], clkb1_shift[11:8]
SPI_WriteData(0x30);
SPI_WriteComm(0xCEc1); // cec2[7:0] : clkb1_shift[7:0]
SPI_WriteData(0x01);
SPI_WriteComm(0xCEc2); // cec3[7:0] : clkb1_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]
SPI_WriteData(0x03);
SPI_WriteComm(0xCEc3); // cec4[7:0] : clkb1_switch[7:0]
SPI_WriteData(0x25);
SPI_WriteComm(0xCEc4); // cec5[7:0] : clkb1_extend[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEc5); // cec6[7:0] : clkb1_tchop[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEc6); // cec7[7:0] : clkb1_tglue[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEc7); // cec8[7:0] : clkb2_width[3:0], clkb2_shift[11:8]
SPI_WriteData(0x30);
SPI_WriteComm(0xCEc8); // cec9[7:0] : clkb2_shift[7:0]
SPI_WriteData(0x02);
SPI_WriteComm(0xCEc9); // ceca[7:0] : clkb2_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]
SPI_WriteData(0x03);
SPI_WriteComm(0xCEca); // cecb[7:0] : clkb2_switch[7:0]
SPI_WriteData(0x26);
SPI_WriteComm(0xCEcb); // cecc[7:0] : clkb2_extend
SPI_WriteData(0x00);
SPI_WriteComm(0xCEcc); // cecd[7:0] : clkb2_tchop
SPI_WriteData(0x00);
SPI_WriteComm(0xCEcd); // cece[7:0] : clkb2_tglue
SPI_WriteData(0x00);
//CEDx : clkb3, clkb4
SPI_WriteComm(0xCEd0); // ced1[7:0] : clkb3_width[3:0], clkb3_shift[11:8]
SPI_WriteData(0x30);
SPI_WriteComm(0xCEd1); // ced2[7:0] : clkb3_shift[7:0]
SPI_WriteData(0x03);
SPI_WriteComm(0xCEd2); // ced3[7:0] : clkb3_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]
SPI_WriteData(0x03);
SPI_WriteComm(0xCEd3); // ced4[7:0] : clkb3_switch[7:0]
SPI_WriteData(0x27);
SPI_WriteComm(0xCEd4); // ced5[7:0] : clkb3_extend[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEd5); // ced6[7:0] : clkb3_tchop[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEd6); // ced7[7:0] : clkb3_tglue[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEd7); // ced8[7:0] : clkb4_width[3:0], clkb4_shift[11:8]
SPI_WriteData(0x30);
SPI_WriteComm(0xCEd8); // ced9[7:0] : clkb4_shift[7:0]
SPI_WriteData(0x04);
SPI_WriteComm(0xCEd9); // ceda[7:0] : clkb4_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]
SPI_WriteData(0x03);
SPI_WriteComm(0xCEda); // cedb[7:0] : clkb4_switch[7:0]
SPI_WriteData(0x28);
SPI_WriteComm(0xCEdb); // cedc[7:0] : clkb4_extend
SPI_WriteData(0x00);
SPI_WriteComm(0xCEdc); // cedd[7:0] : clkb4_tchop
SPI_WriteData(0x00);
SPI_WriteComm(0xCEdd); // cede[7:0] : clkb4_tglue
SPI_WriteData(0x00);
//CFCx :
SPI_WriteComm(0xCFc0); // cfc1[7:0] : eclk_normal_width[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCFc1); // cfc2[7:0] : eclk_partial_width[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCFc2); // cfc3[7:0] : all_normal_tchop[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCFc3); // cfc4[7:0] : all_partial_tchop[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCFc4); // cfc5[7:0] : eclk1_follow[3:0], eclk2_follow[3:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCFc5); // cfc6[7:0] : eclk3_follow[3:0], eclk4_follow[3:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCFc6); // cfc7[7:0] : 00, vstmask, venDMAsk, 00, dir1, dir2 (0=VGL, 1=VGH)
SPI_WriteData(0x00);
SPI_WriteComm(0xCFc7); // cfc8[7:0] : reg_goa_gnd_opt, reg_goa_dpgm_tail_set, reg_goa_f_gating_en, reg_goa_f_odd_gating, toggle_mod1, 2, 3, 4
SPI_WriteData(0x00);
SPI_WriteComm(0xCFc8); // cfc9[7:0] : duty_block[3:0], DGPM[3:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCFc9); // cfca[7:0] : reg_goa_gnd_period[7:0]
SPI_WriteData(0x00);
//CFDx :
SPI_WriteComm(0xCFd0); // cfd1[7:0] : 0000000, reg_goa_frame_odd_high
SPI_WriteData(0x00); // Parameter 1
//--------------------------------------------------------------------------------
// initial setting 3 < Panel setting >
//--------------------------------------------------------------------------------
// cbcx
SPI_WriteComm(0xCBc0); //cbc1[7:0] : enmode H-byte of sig1 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBc1); //cbc2[7:0] : enmode H-byte of sig2 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBc2); //cbc3[7:0] : enmode H-byte of sig3 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBc3); //cbc4[7:0] : enmode H-byte of sig4 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBc4); //cbc5[7:0] : enmode H-byte of sig5 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBc5); //cbc6[7:0] : enmode H-byte of sig6 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBc6); //cbc7[7:0] : enmode H-byte of sig7 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBc7); //cbc8[7:0] : enmode H-byte of sig8 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBc8); //cbc9[7:0] : enmode H-byte of sig9 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBc9); //cbca[7:0] : enmode H-byte of sig10 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBca); //cbcb[7:0] : enmode H-byte of sig11 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBcb); //cbcc[7:0] : enmode H-byte of sig12 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBcc); //cbcd[7:0] : enmode H-byte of sig13 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBcd); //cbce[7:0] : enmode H-byte of sig14 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBce); //cbcf[7:0] : enmode H-byte of sig15 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
// cbdx
SPI_WriteComm(0xCBd0); //cbd1[7:0] : enmode H-byte of sig16 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBd1); //cbd2[7:0] : enmode H-byte of sig17 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBd2); //cbd3[7:0] : enmode H-byte of sig18 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBd3); //cbd4[7:0] : enmode H-byte of sig19 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBd4); //cbd5[7:0] : enmode H-byte of sig20 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBd5); //cbd6[7:0] : enmode H-byte of sig21 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBd6); //cbd7[7:0] : enmode H-byte of sig22 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBd7); //cbd8[7:0] : enmode H-byte of sig23 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBd8); //cbd9[7:0] : enmode H-byte of sig24 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBd9); //cbda[7:0] : enmode H-byte of sig25 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBda); //cbdb[7:0] : enmode H-byte of sig26 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBdb); //cbdc[7:0] : enmode H-byte of sig27 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBdc); //cbdd[7:0] : enmode H-byte of sig28 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBdd); //cbde[7:0] : enmode H-byte of sig29 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBde); //cbdf[7:0] : enmode H-byte of sig30 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
// cbex
SPI_WriteComm(0xCBe0); //cbe1[7:0] : enmode H-byte of sig31 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBe1); //cbe2[7:0] : enmode H-byte of sig32 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBe2); //cbe3[7:0] : enmode H-byte of sig33 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBe3); //cbe4[7:0] : enmode H-byte of sig34 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBe4); //cbe5[7:0] : enmode H-byte of sig35 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBe5); //cbe6[7:0] : enmode H-byte of sig36 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBe6); //cbe7[7:0] : enmode H-byte of sig37 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBe7); //cbe8[7:0] : enmode H-byte of sig38 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBe8); //cbe9[7:0] : enmode H-byte of sig39 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBe9); //cbea[7:0] : enmode H-byte of sig40 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
// cc8x
SPI_WriteComm(0xCC80); //cc81[7:0] : reg setting for signal01 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC81); //cc82[7:0] : reg setting for signal02 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC82); //cc83[7:0] : reg setting for signal03 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC83); //cc84[7:0] : reg setting for signal04 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC84); //cc85[7:0] : reg setting for signal05 selection with u2d mode
SPI_WriteData(0x0C);
SPI_WriteComm(0xCC85); //cc86[7:0] : reg setting for signal06 selection with u2d mode
SPI_WriteData(0x0A);
SPI_WriteComm(0xCC86); //cc87[7:0] : reg setting for signal07 selection with u2d mode
SPI_WriteData(0x10);
SPI_WriteComm(0xCC87); //cc88[7:0] : reg setting for signal08 selection with u2d mode
SPI_WriteData(0x0E);
SPI_WriteComm(0xCC88); //cc89[7:0] : reg setting for signal09 selection with u2d mode
SPI_WriteData(0x03);
SPI_WriteComm(0xCC89); //cc8a[7:0] : reg setting for signal10 selection with u2d mode
SPI_WriteData(0x04);
// cc9x
SPI_WriteComm(0xCC90); //cc91[7:0] : reg setting for signal11 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC91); //cc92[7:0] : reg setting for signal12 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC92); //cc93[7:0] : reg setting for signal13 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC93); //cc94[7:0] : reg setting for signal14 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC94); //cc95[7:0] : reg setting for signal15 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC95); //cc96[7:0] : reg setting for signal16 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC96); //cc97[7:0] : reg setting for signal17 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC97); //cc98[7:0] : reg setting for signal18 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC98); //cc99[7:0] : reg setting for signal19 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC99); //cc9a[7:0] : reg setting for signal20 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC9a); //cc9b[7:0] : reg setting for signal21 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC9b); //cc9c[7:0] : reg setting for signal22 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC9c); //cc9d[7:0] : reg setting for signal23 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC9d); //cc9e[7:0] : reg setting for signal24 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC9e); //cc9f[7:0] : reg setting for signal25 selection with u2d mode
SPI_WriteData(0x0B);
// ccax
SPI_WriteComm(0xCCa0); //cca1[7:0] : reg setting for signal26 selection with u2d mode
SPI_WriteData(0x09);
SPI_WriteComm(0xCCa1); //cca2[7:0] : reg setting for signal27 selection with u2d mode
SPI_WriteData(0x0F);
SPI_WriteComm(0xCCa2); //cca3[7:0] : reg setting for signal28 selection with u2d mode
SPI_WriteData(0x0D);
SPI_WriteComm(0xCCa3); //cca4[7:0] : reg setting for signal29 selection with u2d mode
SPI_WriteData(0x01);
SPI_WriteComm(0xCCa4); //cca5[7:0] : reg setting for signal20 selection with u2d mode
SPI_WriteData(0x02);
SPI_WriteComm(0xCCa5); //cca6[7:0] : reg setting for signal31 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCa6); //cca7[7:0] : reg setting for signal32 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCa7); //cca8[7:0] : reg setting for signal33 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCa8); //cca9[7:0] : reg setting for signal34 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCa9); //ccaa[7:0] : reg setting for signal35 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCaa); //ccab[7:0] : reg setting for signal36 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCab); //ccac[7:0] : reg setting for signal37 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCac); //ccad[7:0] : reg setting for signal38 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCad); //ccae[7:0] : reg setting for signal39 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCae); //ccaf[7:0] : reg setting for signal40 selection with u2d mode
SPI_WriteData(0x00);
// ccbx
SPI_WriteComm(0xCCb0); //ccb1[7:0] : reg setting for signal01 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCb1); //ccb2[7:0] : reg setting for signal02 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCb2); //ccb3[7:0] : reg setting for signal03 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCb3); //ccb4[7:0] : reg setting for signal04 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCb4); //ccb5[7:0] : reg setting for signal05 selection with d2u mode
SPI_WriteData(0x0D);
SPI_WriteComm(0xCCb5); //ccb6[7:0] : reg setting for signal06 selection with d2u mode
SPI_WriteData(0x0F);
SPI_WriteComm(0xCCb6); //ccb7[7:0] : reg setting for signal07 selection with d2u mode
SPI_WriteData(0x09);
SPI_WriteComm(0xCCb7); //ccb8[7:0] : reg setting for signal08 selection with d2u mode
SPI_WriteData(0x0B);
SPI_WriteComm(0xCCb8); //ccb9[7:0] : reg setting for signal09 selection with d2u mode
SPI_WriteData(0x02);
SPI_WriteComm(0xCCb9); //ccba[7:0] : reg setting for signal10 selection with d2u mode
SPI_WriteData(0x01);
// cccx
SPI_WriteComm(0xCCc0); //ccc1[7:0] : reg setting for signal11 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCc1); //ccc2[7:0] : reg setting for signal12 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCc2); //ccc3[7:0] : reg setting for signal13 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCc3); //ccc4[7:0] : reg setting for signal14 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCc4); //ccc5[7:0] : reg setting for signal15 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCc5); //ccc6[7:0] : reg setting for signal16 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCc6); //ccc7[7:0] : reg setting for signal17 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCc7); //ccc8[7:0] : reg setting for signal18 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCc8); //ccc9[7:0] : reg setting for signal19 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCc9); //ccca[7:0] : reg setting for signal20 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCca); //cccb[7:0] : reg setting for signal21 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCcb); //cccc[7:0] : reg setting for signal22 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCcc); //cccd[7:0] : reg setting for signal23 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCcd); //ccce[7:0] : reg setting for signal24 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCce); //cccf[7:0] : reg setting for signal25 selection with d2u mode
SPI_WriteData(0x0E);
// ccdx
SPI_WriteComm(0xCCd0); //ccd1[7:0] : reg setting for signal26 selection with d2u mode
SPI_WriteData(0x10);
SPI_WriteComm(0xCCd1); //ccd2[7:0] : reg setting for signal27 selection with d2u mode
SPI_WriteData(0x0A);
SPI_WriteComm(0xCCd2); //ccd3[7:0] : reg setting for signal28 selection with d2u mode
SPI_WriteData(0x0C);
SPI_WriteComm(0xCCd3); //ccd4[7:0] : reg setting for signal29 selection with d2u mode
SPI_WriteData(0x04);
SPI_WriteComm(0xCCd4); //ccd5[7:0] : reg setting for signal30 selection with d2u mode
SPI_WriteData(0x03);
SPI_WriteComm(0xCCd5); //ccd6[7:0] : reg setting for signal31 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCd6); //ccd7[7:0] : reg setting for signal32 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCd7); //ccd8[7:0] : reg setting for signal33 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCd8); //ccd9[7:0] : reg setting for signal34 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCd9); //ccda[7:0] : reg setting for signal35 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCda); //ccdb[7:0] : reg setting for signal36 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCdb); //ccdc[7:0] : reg setting for signal37 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCdc); //ccdd[7:0] : reg setting for signal38 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCdd); //ccde[7:0] : reg setting for signal39 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCde); //ccdf[7:0] : reg setting for signal40 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0x3A77); // RGB 18bits D[17:0]
SPI_WriteData(0x77);
SPI_WriteComm(0x1100);
delay_ms(12);
SPI_WriteComm(0x2900);
delay_ms(5);
}
#include "delay.h"
#define SPI_WriteComm LCD_WR_REG_SPI
#define SPI_WriteData LCD_WR_DATA_SPI
#define Delay delay_ms
void LCM_Initcode(void)
{
LCD_SPI_Reset();
/*
//ivo463
SPI_WriteComm(0xFF00); SPI_WriteData(0x80);
SPI_WriteComm(0xFF01); SPI_WriteData(0x09);
SPI_WriteComm(0xFF02); SPI_WriteData(0x01);
SPI_WriteComm(0xFF80); SPI_WriteData(0x80);
SPI_WriteComm(0xFF81); SPI_WriteData(0x09);
SPI_WriteComm(0xC0B4); SPI_WriteData(0x50);
SPI_WriteComm(0xC582); SPI_WriteData(0xA3);
SPI_WriteComm(0xC590); SPI_WriteData(0x96);
SPI_WriteComm(0xC591); SPI_WriteData(0x87);
SPI_WriteComm(0xD800); SPI_WriteData(0x87);
SPI_WriteComm(0xD801); SPI_WriteData(0x87);
SPI_WriteComm(0xD900); SPI_WriteData(0x4E);
SPI_WriteComm(0xC181); SPI_WriteData(0x66);
SPI_WriteComm(0xC1A0); SPI_WriteData(0xEA);
SPI_WriteComm(0xC1A1); SPI_WriteData(0x08);
SPI_WriteComm(0xC489); SPI_WriteData(0x08);
SPI_WriteComm(0xC0A3); SPI_WriteData(0x00);
SPI_WriteComm(0xC481); SPI_WriteData(0x83);
SPI_WriteComm(0xC592); SPI_WriteData(0x01);
SPI_WriteComm(0xC5B1); SPI_WriteData(0xA9);
SPI_WriteComm(0xCFC7); SPI_WriteData(0x02);
SPI_WriteComm(0xB390); SPI_WriteData(0x02);
SPI_WriteComm(0xB392); SPI_WriteData(0x45);
SPI_WriteComm(0xC080); SPI_WriteData(0x00);
SPI_WriteComm(0xC081); SPI_WriteData(0x58);
SPI_WriteComm(0xC082); SPI_WriteData(0x00);
SPI_WriteComm(0xC083); SPI_WriteData(0x15);
SPI_WriteComm(0xC084); SPI_WriteData(0x15);
SPI_WriteComm(0xC085); SPI_WriteData(0x00);
SPI_WriteComm(0xC086); SPI_WriteData(0x58);
SPI_WriteComm(0xC087); SPI_WriteData(0x15);
SPI_WriteComm(0xC088); SPI_WriteData(0x15);
SPI_WriteComm(0xC090); SPI_WriteData(0x00);
SPI_WriteComm(0xC091); SPI_WriteData(0x44);
SPI_WriteComm(0xC092); SPI_WriteData(0x00);
SPI_WriteComm(0xC093); SPI_WriteData(0x00);
SPI_WriteComm(0xC094); SPI_WriteData(0x00);
SPI_WriteComm(0xC095); SPI_WriteData(0x03);
SPI_WriteComm(0xC1A6); SPI_WriteData(0x01);
SPI_WriteComm(0xC1A7); SPI_WriteData(0x00);
SPI_WriteComm(0xC1A8); SPI_WriteData(0x00);
SPI_WriteComm(0xCE80); SPI_WriteData(0x87);
SPI_WriteComm(0xCE81); SPI_WriteData(0x03);
SPI_WriteComm(0xCE82); SPI_WriteData(0x00);
SPI_WriteComm(0xCE83); SPI_WriteData(0x86);
SPI_WriteComm(0xCE84); SPI_WriteData(0x03);
SPI_WriteComm(0xCE85); SPI_WriteData(0x00);
SPI_WriteComm(0xCE86); SPI_WriteData(0x85);
SPI_WriteComm(0xCE87); SPI_WriteData(0x03);
SPI_WriteComm(0xCE88); SPI_WriteData(0x00);
SPI_WriteComm(0xCE89); SPI_WriteData(0x84);
SPI_WriteComm(0xCE8A); SPI_WriteData(0x03);
SPI_WriteComm(0xCE8B); SPI_WriteData(0x00);
SPI_WriteComm(0xCE90); SPI_WriteData(0x33);
SPI_WriteComm(0xCE91); SPI_WriteData(0x52);
SPI_WriteComm(0xCE92); SPI_WriteData(0x00);
SPI_WriteComm(0xCE93); SPI_WriteData(0x33);
SPI_WriteComm(0xCE94); SPI_WriteData(0x53);
SPI_WriteComm(0xCE95); SPI_WriteData(0x00);
SPI_WriteComm(0xCE96); SPI_WriteData(0x33);
SPI_WriteComm(0xCE97); SPI_WriteData(0x54);
SPI_WriteComm(0xCE98); SPI_WriteData(0x00);
SPI_WriteComm(0xCE99); SPI_WriteData(0x33);
SPI_WriteComm(0xCE9A); SPI_WriteData(0x55);
SPI_WriteComm(0xCE9B); SPI_WriteData(0x00);
SPI_WriteComm(0xCE9C); SPI_WriteData(0x00);
SPI_WriteComm(0xCE9D); SPI_WriteData(0x00);
SPI_WriteComm(0xCEA0); SPI_WriteData(0x38);
SPI_WriteComm(0xCEA1); SPI_WriteData(0x05);
SPI_WriteComm(0xCEA2); SPI_WriteData(0x03);
SPI_WriteComm(0xCEA3); SPI_WriteData(0x56);
SPI_WriteComm(0xCEA4); SPI_WriteData(0x00);
SPI_WriteComm(0xCEA5); SPI_WriteData(0x00);
SPI_WriteComm(0xCEA6); SPI_WriteData(0x00);
SPI_WriteComm(0xCEA7); SPI_WriteData(0x38);
SPI_WriteComm(0xCEA8); SPI_WriteData(0x04);
SPI_WriteComm(0xCEA9); SPI_WriteData(0x03);
SPI_WriteComm(0xCEAA); SPI_WriteData(0x57);
SPI_WriteComm(0xCEAB); SPI_WriteData(0x00);
SPI_WriteComm(0xCEAC); SPI_WriteData(0x00);
SPI_WriteComm(0xCEAD); SPI_WriteData(0x00);
SPI_WriteComm(0xCEB0); SPI_WriteData(0x38);
SPI_WriteComm(0xCEB1); SPI_WriteData(0x03);
SPI_WriteComm(0xCEB2); SPI_WriteData(0x03);
SPI_WriteComm(0xCEB3); SPI_WriteData(0x58);
SPI_WriteComm(0xCEB4); SPI_WriteData(0x00);
SPI_WriteComm(0xCEB5); SPI_WriteData(0x00);
SPI_WriteComm(0xCEB6); SPI_WriteData(0x00);
SPI_WriteComm(0xCEB7); SPI_WriteData(0x38);
SPI_WriteComm(0xCEB8); SPI_WriteData(0x02);
SPI_WriteComm(0xCEB9); SPI_WriteData(0x03);
SPI_WriteComm(0xCEBA); SPI_WriteData(0x59);
SPI_WriteComm(0xCEBB); SPI_WriteData(0x00);
SPI_WriteComm(0xCEBC); SPI_WriteData(0x00);
SPI_WriteComm(0xCEBD); SPI_WriteData(0x00);
SPI_WriteComm(0xCEC0); SPI_WriteData(0x38);
SPI_WriteComm(0xCEC1); SPI_WriteData(0x01);
SPI_WriteComm(0xCEC2); SPI_WriteData(0x03);
SPI_WriteComm(0xCEC3); SPI_WriteData(0x5A);
SPI_WriteComm(0xCEC4); SPI_WriteData(0x00);
SPI_WriteComm(0xCEC5); SPI_WriteData(0x00);
SPI_WriteComm(0xCEC6); SPI_WriteData(0x00);
SPI_WriteComm(0xCEC7); SPI_WriteData(0x38);
SPI_WriteComm(0xCEC8); SPI_WriteData(0x00);
SPI_WriteComm(0xCEC9); SPI_WriteData(0x03);
SPI_WriteComm(0xCECA); SPI_WriteData(0x5C);
SPI_WriteComm(0xCECB); SPI_WriteData(0x00);
SPI_WriteComm(0xCECC); SPI_WriteData(0x00);
SPI_WriteComm(0xCECD); SPI_WriteData(0x00);
SPI_WriteComm(0xCED0); SPI_WriteData(0X30);
SPI_WriteComm(0xCED1); SPI_WriteData(0x00);
SPI_WriteComm(0xCED2); SPI_WriteData(0x03);
SPI_WriteComm(0xCED3); SPI_WriteData(0x5C);
SPI_WriteComm(0xCED4); SPI_WriteData(0x00);
SPI_WriteComm(0xCED5); SPI_WriteData(0x00);
SPI_WriteComm(0xCED6); SPI_WriteData(0x00);
SPI_WriteComm(0xCED7); SPI_WriteData(0x30);
SPI_WriteComm(0xCED8); SPI_WriteData(0x01);
SPI_WriteComm(0xCED9); SPI_WriteData(0x03);
SPI_WriteComm(0xCEDA); SPI_WriteData(0x5D);
SPI_WriteComm(0xCEDB); SPI_WriteData(0x00);
SPI_WriteComm(0xCEDC); SPI_WriteData(0x00);
SPI_WriteComm(0xCEDD); SPI_WriteData(0x00);
SPI_WriteComm(0xCBC3); SPI_WriteData(0x04);
SPI_WriteComm(0xCBC4); SPI_WriteData(0x04);
SPI_WriteComm(0xCBC5); SPI_WriteData(0x04);
SPI_WriteComm(0xCBC6); SPI_WriteData(0x04);
SPI_WriteComm(0xCBC7); SPI_WriteData(0x04);
SPI_WriteComm(0xCBC8); SPI_WriteData(0x04);
SPI_WriteComm(0xCBC9); SPI_WriteData(0x04);
SPI_WriteComm(0xCBCA); SPI_WriteData(0x04);
SPI_WriteComm(0xCBD8); SPI_WriteData(0x04);
SPI_WriteComm(0xCBD9); SPI_WriteData(0x04);
SPI_WriteComm(0xCBDA); SPI_WriteData(0x04);
SPI_WriteComm(0xCBDB); SPI_WriteData(0x04);
SPI_WriteComm(0xCBDC); SPI_WriteData(0x04);
SPI_WriteComm(0xCBDD); SPI_WriteData(0x04);
SPI_WriteComm(0xCBDE); SPI_WriteData(0x04);
SPI_WriteComm(0xCBE0); SPI_WriteData(0x04);
SPI_WriteComm(0xCC83); SPI_WriteData(0x03);
SPI_WriteComm(0xCC84); SPI_WriteData(0x01);
SPI_WriteComm(0xCC85); SPI_WriteData(0x09);
SPI_WriteComm(0xCC86); SPI_WriteData(0x0B);
SPI_WriteComm(0xCC87); SPI_WriteData(0x0D);
SPI_WriteComm(0xCC88); SPI_WriteData(0x0F);
SPI_WriteComm(0xCC89); SPI_WriteData(0x05);
SPI_WriteComm(0xCC90); SPI_WriteData(0x07);
SPI_WriteComm(0xCC9D); SPI_WriteData(0x04);
SPI_WriteComm(0xCC9E); SPI_WriteData(0x02);
SPI_WriteComm(0xCCA0); SPI_WriteData(0x0A);
SPI_WriteComm(0xCCA1); SPI_WriteData(0x0C);
SPI_WriteComm(0xCCA2); SPI_WriteData(0x0E);
SPI_WriteComm(0xCCA3); SPI_WriteData(0x10);
SPI_WriteComm(0xCCA4); SPI_WriteData(0x06);
SPI_WriteComm(0xCCA5); SPI_WriteData(0x08);
SPI_WriteComm(0xCCB3); SPI_WriteData(0x06);
SPI_WriteComm(0xCCB4); SPI_WriteData(0x08);
SPI_WriteComm(0xCCB5); SPI_WriteData(0x0A);
SPI_WriteComm(0xCCB6); SPI_WriteData(0x10);
SPI_WriteComm(0xCCB7); SPI_WriteData(0x0E);
SPI_WriteComm(0xCCB8); SPI_WriteData(0x0C);
SPI_WriteComm(0xCCB9); SPI_WriteData(0x04);
SPI_WriteComm(0xCCC0); SPI_WriteData(0x02);
SPI_WriteComm(0xCCCD); SPI_WriteData(0x05);
SPI_WriteComm(0xCCCE); SPI_WriteData(0x07);
SPI_WriteComm(0xCCD0); SPI_WriteData(0x09);
SPI_WriteComm(0xCCD1); SPI_WriteData(0x0F);
SPI_WriteComm(0xCCD2); SPI_WriteData(0x0D);
SPI_WriteComm(0xCCD3); SPI_WriteData(0x0B);
SPI_WriteComm(0xCCD4); SPI_WriteData(0x03);
SPI_WriteComm(0xCCD5); SPI_WriteData(0x01);
SPI_WriteComm(0xE100); SPI_WriteData(0x04);
SPI_WriteComm(0xE101); SPI_WriteData(0x0D);
SPI_WriteComm(0xE102); SPI_WriteData(0x12);
SPI_WriteComm(0xE103); SPI_WriteData(0x0F);
SPI_WriteComm(0xE104); SPI_WriteData(0x09);
SPI_WriteComm(0xE105); SPI_WriteData(0x1C);
SPI_WriteComm(0xE106); SPI_WriteData(0x0E);
SPI_WriteComm(0xE107); SPI_WriteData(0x0E);
SPI_WriteComm(0xE108); SPI_WriteData(0x00);
SPI_WriteComm(0xE109); SPI_WriteData(0x05);
SPI_WriteComm(0xE10A); SPI_WriteData(0x02);
SPI_WriteComm(0xE10B); SPI_WriteData(0x06);
SPI_WriteComm(0xE10C); SPI_WriteData(0x0E);
SPI_WriteComm(0xE10D); SPI_WriteData(0x1D);
SPI_WriteComm(0xE10E); SPI_WriteData(0x1A);
SPI_WriteComm(0xE10F); SPI_WriteData(0x12);
SPI_WriteComm(0xE200); SPI_WriteData(0x04);
SPI_WriteComm(0xE201); SPI_WriteData(0x0D);
SPI_WriteComm(0xE202); SPI_WriteData(0x12);
SPI_WriteComm(0xE203); SPI_WriteData(0x0E);
SPI_WriteComm(0xE204); SPI_WriteData(0x08);
SPI_WriteComm(0xE205); SPI_WriteData(0x1C);
SPI_WriteComm(0xE206); SPI_WriteData(0x0E);
SPI_WriteComm(0xE207); SPI_WriteData(0x0E);
SPI_WriteComm(0xE208); SPI_WriteData(0x00);
SPI_WriteComm(0xE209); SPI_WriteData(0x04);
SPI_WriteComm(0xE20A); SPI_WriteData(0x03);
SPI_WriteComm(0xE20B); SPI_WriteData(0x07);
SPI_WriteComm(0xE20C); SPI_WriteData(0x0E);
SPI_WriteComm(0xE20D); SPI_WriteData(0x1E);
SPI_WriteComm(0xE20E); SPI_WriteData(0x1B);
SPI_WriteComm(0xE20F); SPI_WriteData(0x12);
SPI_WriteComm(0xFF00); SPI_WriteData(0xFF);
SPI_WriteComm(0xFF01); SPI_WriteData(0xFF);
SPI_WriteComm(0xFF02); SPI_WriteData(0xFF);
SPI_WriteComm(0x3A00); SPI_WriteData(0x77);
SPI_WriteComm(0x1100);
Delay(120);
SPI_WriteComm(0x2900);
*/
//hsd4.3
SPI_WriteComm(0xff00); //
SPI_WriteData(0x80);
SPI_WriteComm(0xff01); // enable EXTC
SPI_WriteData(0x09);
SPI_WriteComm(0xff02); //
SPI_WriteData(0x01);
SPI_WriteComm(0xff80); // enable Orise mode
SPI_WriteData(0x80);
SPI_WriteComm(0xff81); //
SPI_WriteData(0x09);
SPI_WriteComm(0xff03); // enable SPI+I2C cmd2 read
SPI_WriteData(0x01);
//gamma DC
SPI_WriteComm(0xc0b4); //1+2dot inversion
SPI_WriteData(0x10);
SPI_WriteComm(0xC489); //reg off
SPI_WriteData(0x08);
SPI_WriteComm(0xC0a3); //pre-charge //V02
SPI_WriteData(0x00);
SPI_WriteComm(0xC582); //REG-pump23
SPI_WriteData(0xA3);
SPI_WriteComm(0xC590); //Pump setting (3x=D6)-->(2x=96)//v02 01/11
SPI_WriteData(0xd6);
SPI_WriteComm(0xC591); //Pump setting(VGH/VGL)
SPI_WriteData(0x87);
SPI_WriteComm(0xD800); //GVDD=4.5V
SPI_WriteData(0x74);
SPI_WriteComm(0xD801); //NGVDD=4.5V
SPI_WriteData(0x72);
//VCOMDC
SPI_WriteComm(0xd900); // VCOMDC=
SPI_WriteData(0x60);
SPI_WriteComm(0xE100); SPI_WriteData(0x09);
SPI_WriteComm(0xE101); SPI_WriteData(0x0a);
SPI_WriteComm(0xE102); SPI_WriteData(0x0e);
SPI_WriteComm(0xE103); SPI_WriteData(0x0d);
SPI_WriteComm(0xE104); SPI_WriteData(0x07);
SPI_WriteComm(0xE105); SPI_WriteData(0x18);
SPI_WriteComm(0xE106); SPI_WriteData(0x0d);
SPI_WriteComm(0xE107); SPI_WriteData(0x0d);
SPI_WriteComm(0xE108); SPI_WriteData(0x01);
SPI_WriteComm(0xE109); SPI_WriteData(0x04);
SPI_WriteComm(0xE10A); SPI_WriteData(0x05);
SPI_WriteComm(0xE10B); SPI_WriteData(0x06);
SPI_WriteComm(0xE10C); SPI_WriteData(0x0e);
SPI_WriteComm(0xE10D); SPI_WriteData(0x25);
SPI_WriteComm(0xE10E); SPI_WriteData(0x22);
SPI_WriteComm(0xE10F); SPI_WriteData(0x05);
// Negative
SPI_WriteComm(0xE200); SPI_WriteData(0x09);
SPI_WriteComm(0xE201); SPI_WriteData(0x0a);
SPI_WriteComm(0xE202); SPI_WriteData(0x0e);
SPI_WriteComm(0xE203); SPI_WriteData(0x0d);
SPI_WriteComm(0xE204); SPI_WriteData(0x07);
SPI_WriteComm(0xE205); SPI_WriteData(0x18);
SPI_WriteComm(0xE206); SPI_WriteData(0x0d);
SPI_WriteComm(0xE207); SPI_WriteData(0x0d);
SPI_WriteComm(0xE208); SPI_WriteData(0x01);
SPI_WriteComm(0xE209); SPI_WriteData(0x04);
SPI_WriteComm(0xE20A); SPI_WriteData(0x05);
SPI_WriteComm(0xE20B); SPI_WriteData(0x06);
SPI_WriteComm(0xE20C); SPI_WriteData(0x0e);
SPI_WriteComm(0xE20D); SPI_WriteData(0x25);
SPI_WriteComm(0xE20E); SPI_WriteData(0x22);
SPI_WriteComm(0xE20F); SPI_WriteData(0x05);
SPI_WriteComm(0xC181); //Frame rate 65Hz//V02
SPI_WriteData(0x66);
// RGB I/F setting VSYNC for OTM8018 0x0e
SPI_WriteComm(0xC1a1); //external Vsync(08) /Vsync,Hsync(0c) /Vsync,Hsync,DE(0e) //V02(0e) / all included clk(0f)
SPI_WriteData(0x08);
//SPI_WriteComm(0xC0a3); //pre-charge //V02
//SPI_WriteData(0x1b);
SPI_WriteComm(0xC481); //source bias //V02
SPI_WriteData(0x83);
SPI_WriteComm(0xC592); //Pump45
SPI_WriteData(0x01);//(01)
SPI_WriteComm(0xC5B1); //DC voltage setting ;[0]GVDD output, default: 0xa8
SPI_WriteData(0xA9);
SPI_WriteComm(0xC480); //no-display Source output = GND
SPI_WriteData(0x30);
//--------------------------------------------------------------------------------
// initial setting 2 < tcon_goa_wave >
//--------------------------------------------------------------------------------
// CE8x : vst1, vst2, vst3, vst4
SPI_WriteComm(0xCE80); // ce81[7:0] : vst1_shift[7:0]
SPI_WriteData(0x85);
SPI_WriteComm(0xCE81); // ce82[7:0] : 0000, vst1_width[3:0]
SPI_WriteData(0x03);
SPI_WriteComm(0xCE82); // ce83[7:0] : vst1_tchop[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCE83); // ce84[7:0] : vst2_shift[7:0]
SPI_WriteData(0x84);
SPI_WriteComm(0xCE84); // ce85[7:0] : 0000, vst2_width[3:0]
SPI_WriteData(0x03);
SPI_WriteComm(0xCE85); // ce86[7:0] : vst2_tchop[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCE86); // ce87[7:0] : vst3_shift[7:0]
SPI_WriteData(0x83);
SPI_WriteComm(0xCE87); // ce88[7:0] : 0000, vst3_width[3:0]
SPI_WriteData(0x03);
SPI_WriteComm(0xCE88); // ce89[7:0] : vst3_tchop[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCE89); // ce8a[7:0] : vst4_shift[7:0]
SPI_WriteData(0x82);
SPI_WriteComm(0xCE8a); // ce8b[7:0] : 0000, vst4_width[3:0]
SPI_WriteData(0x03);
SPI_WriteComm(0xCE8b); // ce8c[7:0] : vst4_tchop[7:0]
SPI_WriteData(0x00);
//CEAx : clka1, clka2
SPI_WriteComm(0xCEa0); // cea1[7:0] : clka1_width[3:0], clka1_shift[11:8]
SPI_WriteData(0x38);
SPI_WriteComm(0xCEa1); // cea2[7:0] : clka1_shift[7:0]
SPI_WriteData(0x02);
SPI_WriteComm(0xCEa2); // cea3[7:0] : clka1_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]
SPI_WriteData(0x03);
SPI_WriteComm(0xCEa3); // cea4[7:0] : clka1_switch[7:0]
SPI_WriteData(0x21);
SPI_WriteComm(0xCEa4); // cea5[7:0] : clka1_extend[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEa5); // cea6[7:0] : clka1_tchop[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEa6); // cea7[7:0] : clka1_tglue[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEa7); // cea8[7:0] : clka2_width[3:0], clka2_shift[11:8]
SPI_WriteData(0x38);
SPI_WriteComm(0xCEa8); // cea9[7:0] : clka2_shift[7:0]
SPI_WriteData(0x01);
SPI_WriteComm(0xCEa9); // ceaa[7:0] : clka2_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]
SPI_WriteData(0x03);
SPI_WriteComm(0xCEaa); // ceab[7:0] : clka2_switch[7:0]
SPI_WriteData(0x22);
SPI_WriteComm(0xCEab); // ceac[7:0] : clka2_extend
SPI_WriteData(0x00);
SPI_WriteComm(0xCEac); // cead[7:0] : clka2_tchop
SPI_WriteData(0x00);
SPI_WriteComm(0xCEad); // ceae[7:0] : clka2_tglue
SPI_WriteData(0x00);
//CEBx : clka3, clka4
SPI_WriteComm(0xCEb0); // ceb1[7:0] : clka3_width[3:0], clka3_shift[11:8]
SPI_WriteData(0x38);
SPI_WriteComm(0xCEb1); // ceb2[7:0] : clka3_shift[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEb2); // ceb3[7:0] : clka3_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]
SPI_WriteData(0x03);
SPI_WriteComm(0xCEb3); // ceb4[7:0] : clka3_switch[7:0]
SPI_WriteData(0x23);
SPI_WriteComm(0xCEb4); // ceb5[7:0] : clka3_extend[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEb5); // ceb6[7:0] : clka3_tchop[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEb6); // ceb7[7:0] : clka3_tglue[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEb7); // ceb8[7:0] : clka4_width[3:0], clka2_shift[11:8]
SPI_WriteData(0x30);
SPI_WriteComm(0xCEb8); // ceb9[7:0] : clka4_shift[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEb9); // ceba[7:0] : clka4_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]
SPI_WriteData(0x03);
SPI_WriteComm(0xCEba); // cebb[7:0] : clka4_switch[7:0]
SPI_WriteData(0x24);
SPI_WriteComm(0xCEbb); // cebc[7:0] : clka4_extend
SPI_WriteData(0x00);
SPI_WriteComm(0xCEbc); // cebd[7:0] : clka4_tchop
SPI_WriteData(0x00);
SPI_WriteComm(0xCEbd); // cebe[7:0] : clka4_tglue
SPI_WriteData(0x00);
//CECx : clkb1, clkb2
SPI_WriteComm(0xCEc0); // cec1[7:0] : clkb1_width[3:0], clkb1_shift[11:8]
SPI_WriteData(0x30);
SPI_WriteComm(0xCEc1); // cec2[7:0] : clkb1_shift[7:0]
SPI_WriteData(0x01);
SPI_WriteComm(0xCEc2); // cec3[7:0] : clkb1_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]
SPI_WriteData(0x03);
SPI_WriteComm(0xCEc3); // cec4[7:0] : clkb1_switch[7:0]
SPI_WriteData(0x25);
SPI_WriteComm(0xCEc4); // cec5[7:0] : clkb1_extend[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEc5); // cec6[7:0] : clkb1_tchop[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEc6); // cec7[7:0] : clkb1_tglue[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEc7); // cec8[7:0] : clkb2_width[3:0], clkb2_shift[11:8]
SPI_WriteData(0x30);
SPI_WriteComm(0xCEc8); // cec9[7:0] : clkb2_shift[7:0]
SPI_WriteData(0x02);
SPI_WriteComm(0xCEc9); // ceca[7:0] : clkb2_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]
SPI_WriteData(0x03);
SPI_WriteComm(0xCEca); // cecb[7:0] : clkb2_switch[7:0]
SPI_WriteData(0x26);
SPI_WriteComm(0xCEcb); // cecc[7:0] : clkb2_extend
SPI_WriteData(0x00);
SPI_WriteComm(0xCEcc); // cecd[7:0] : clkb2_tchop
SPI_WriteData(0x00);
SPI_WriteComm(0xCEcd); // cece[7:0] : clkb2_tglue
SPI_WriteData(0x00);
//CEDx : clkb3, clkb4
SPI_WriteComm(0xCEd0); // ced1[7:0] : clkb3_width[3:0], clkb3_shift[11:8]
SPI_WriteData(0x30);
SPI_WriteComm(0xCEd1); // ced2[7:0] : clkb3_shift[7:0]
SPI_WriteData(0x03);
SPI_WriteComm(0xCEd2); // ced3[7:0] : clkb3_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]
SPI_WriteData(0x03);
SPI_WriteComm(0xCEd3); // ced4[7:0] : clkb3_switch[7:0]
SPI_WriteData(0x27);
SPI_WriteComm(0xCEd4); // ced5[7:0] : clkb3_extend[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEd5); // ced6[7:0] : clkb3_tchop[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEd6); // ced7[7:0] : clkb3_tglue[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCEd7); // ced8[7:0] : clkb4_width[3:0], clkb4_shift[11:8]
SPI_WriteData(0x30);
SPI_WriteComm(0xCEd8); // ced9[7:0] : clkb4_shift[7:0]
SPI_WriteData(0x04);
SPI_WriteComm(0xCEd9); // ceda[7:0] : clkb4_sw_tg, odd_high, flat_head, flat_tail, switch[11:8]
SPI_WriteData(0x03);
SPI_WriteComm(0xCEda); // cedb[7:0] : clkb4_switch[7:0]
SPI_WriteData(0x28);
SPI_WriteComm(0xCEdb); // cedc[7:0] : clkb4_extend
SPI_WriteData(0x00);
SPI_WriteComm(0xCEdc); // cedd[7:0] : clkb4_tchop
SPI_WriteData(0x00);
SPI_WriteComm(0xCEdd); // cede[7:0] : clkb4_tglue
SPI_WriteData(0x00);
//CFCx :
SPI_WriteComm(0xCFc0); // cfc1[7:0] : eclk_normal_width[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCFc1); // cfc2[7:0] : eclk_partial_width[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCFc2); // cfc3[7:0] : all_normal_tchop[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCFc3); // cfc4[7:0] : all_partial_tchop[7:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCFc4); // cfc5[7:0] : eclk1_follow[3:0], eclk2_follow[3:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCFc5); // cfc6[7:0] : eclk3_follow[3:0], eclk4_follow[3:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCFc6); // cfc7[7:0] : 00, vstmask, venDMAsk, 00, dir1, dir2 (0=VGL, 1=VGH)
SPI_WriteData(0x00);
SPI_WriteComm(0xCFc7); // cfc8[7:0] : reg_goa_gnd_opt, reg_goa_dpgm_tail_set, reg_goa_f_gating_en, reg_goa_f_odd_gating, toggle_mod1, 2, 3, 4
SPI_WriteData(0x00);
SPI_WriteComm(0xCFc8); // cfc9[7:0] : duty_block[3:0], DGPM[3:0]
SPI_WriteData(0x00);
SPI_WriteComm(0xCFc9); // cfca[7:0] : reg_goa_gnd_period[7:0]
SPI_WriteData(0x00);
//CFDx :
SPI_WriteComm(0xCFd0); // cfd1[7:0] : 0000000, reg_goa_frame_odd_high
SPI_WriteData(0x00); // Parameter 1
//--------------------------------------------------------------------------------
// initial setting 3 < Panel setting >
//--------------------------------------------------------------------------------
// cbcx
SPI_WriteComm(0xCBc0); //cbc1[7:0] : enmode H-byte of sig1 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBc1); //cbc2[7:0] : enmode H-byte of sig2 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBc2); //cbc3[7:0] : enmode H-byte of sig3 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBc3); //cbc4[7:0] : enmode H-byte of sig4 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBc4); //cbc5[7:0] : enmode H-byte of sig5 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBc5); //cbc6[7:0] : enmode H-byte of sig6 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBc6); //cbc7[7:0] : enmode H-byte of sig7 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBc7); //cbc8[7:0] : enmode H-byte of sig8 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBc8); //cbc9[7:0] : enmode H-byte of sig9 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBc9); //cbca[7:0] : enmode H-byte of sig10 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBca); //cbcb[7:0] : enmode H-byte of sig11 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBcb); //cbcc[7:0] : enmode H-byte of sig12 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBcc); //cbcd[7:0] : enmode H-byte of sig13 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBcd); //cbce[7:0] : enmode H-byte of sig14 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBce); //cbcf[7:0] : enmode H-byte of sig15 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
// cbdx
SPI_WriteComm(0xCBd0); //cbd1[7:0] : enmode H-byte of sig16 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBd1); //cbd2[7:0] : enmode H-byte of sig17 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBd2); //cbd3[7:0] : enmode H-byte of sig18 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBd3); //cbd4[7:0] : enmode H-byte of sig19 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBd4); //cbd5[7:0] : enmode H-byte of sig20 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBd5); //cbd6[7:0] : enmode H-byte of sig21 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBd6); //cbd7[7:0] : enmode H-byte of sig22 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBd7); //cbd8[7:0] : enmode H-byte of sig23 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBd8); //cbd9[7:0] : enmode H-byte of sig24 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBd9); //cbda[7:0] : enmode H-byte of sig25 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBda); //cbdb[7:0] : enmode H-byte of sig26 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBdb); //cbdc[7:0] : enmode H-byte of sig27 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBdc); //cbdd[7:0] : enmode H-byte of sig28 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBdd); //cbde[7:0] : enmode H-byte of sig29 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
SPI_WriteComm(0xCBde); //cbdf[7:0] : enmode H-byte of sig30 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x04);
// cbex
SPI_WriteComm(0xCBe0); //cbe1[7:0] : enmode H-byte of sig31 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBe1); //cbe2[7:0] : enmode H-byte of sig32 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBe2); //cbe3[7:0] : enmode H-byte of sig33 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBe3); //cbe4[7:0] : enmode H-byte of sig34 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBe4); //cbe5[7:0] : enmode H-byte of sig35 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBe5); //cbe6[7:0] : enmode H-byte of sig36 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBe6); //cbe7[7:0] : enmode H-byte of sig37 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBe7); //cbe8[7:0] : enmode H-byte of sig38 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBe8); //cbe9[7:0] : enmode H-byte of sig39 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
SPI_WriteComm(0xCBe9); //cbea[7:0] : enmode H-byte of sig40 (pwrof_0, pwrof_1, norm, pwron_4 )
SPI_WriteData(0x00);
// cc8x
SPI_WriteComm(0xCC80); //cc81[7:0] : reg setting for signal01 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC81); //cc82[7:0] : reg setting for signal02 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC82); //cc83[7:0] : reg setting for signal03 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC83); //cc84[7:0] : reg setting for signal04 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC84); //cc85[7:0] : reg setting for signal05 selection with u2d mode
SPI_WriteData(0x0C);
SPI_WriteComm(0xCC85); //cc86[7:0] : reg setting for signal06 selection with u2d mode
SPI_WriteData(0x0A);
SPI_WriteComm(0xCC86); //cc87[7:0] : reg setting for signal07 selection with u2d mode
SPI_WriteData(0x10);
SPI_WriteComm(0xCC87); //cc88[7:0] : reg setting for signal08 selection with u2d mode
SPI_WriteData(0x0E);
SPI_WriteComm(0xCC88); //cc89[7:0] : reg setting for signal09 selection with u2d mode
SPI_WriteData(0x03);
SPI_WriteComm(0xCC89); //cc8a[7:0] : reg setting for signal10 selection with u2d mode
SPI_WriteData(0x04);
// cc9x
SPI_WriteComm(0xCC90); //cc91[7:0] : reg setting for signal11 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC91); //cc92[7:0] : reg setting for signal12 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC92); //cc93[7:0] : reg setting for signal13 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC93); //cc94[7:0] : reg setting for signal14 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC94); //cc95[7:0] : reg setting for signal15 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC95); //cc96[7:0] : reg setting for signal16 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC96); //cc97[7:0] : reg setting for signal17 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC97); //cc98[7:0] : reg setting for signal18 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC98); //cc99[7:0] : reg setting for signal19 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC99); //cc9a[7:0] : reg setting for signal20 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC9a); //cc9b[7:0] : reg setting for signal21 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC9b); //cc9c[7:0] : reg setting for signal22 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC9c); //cc9d[7:0] : reg setting for signal23 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC9d); //cc9e[7:0] : reg setting for signal24 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCC9e); //cc9f[7:0] : reg setting for signal25 selection with u2d mode
SPI_WriteData(0x0B);
// ccax
SPI_WriteComm(0xCCa0); //cca1[7:0] : reg setting for signal26 selection with u2d mode
SPI_WriteData(0x09);
SPI_WriteComm(0xCCa1); //cca2[7:0] : reg setting for signal27 selection with u2d mode
SPI_WriteData(0x0F);
SPI_WriteComm(0xCCa2); //cca3[7:0] : reg setting for signal28 selection with u2d mode
SPI_WriteData(0x0D);
SPI_WriteComm(0xCCa3); //cca4[7:0] : reg setting for signal29 selection with u2d mode
SPI_WriteData(0x01);
SPI_WriteComm(0xCCa4); //cca5[7:0] : reg setting for signal20 selection with u2d mode
SPI_WriteData(0x02);
SPI_WriteComm(0xCCa5); //cca6[7:0] : reg setting for signal31 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCa6); //cca7[7:0] : reg setting for signal32 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCa7); //cca8[7:0] : reg setting for signal33 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCa8); //cca9[7:0] : reg setting for signal34 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCa9); //ccaa[7:0] : reg setting for signal35 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCaa); //ccab[7:0] : reg setting for signal36 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCab); //ccac[7:0] : reg setting for signal37 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCac); //ccad[7:0] : reg setting for signal38 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCad); //ccae[7:0] : reg setting for signal39 selection with u2d mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCae); //ccaf[7:0] : reg setting for signal40 selection with u2d mode
SPI_WriteData(0x00);
// ccbx
SPI_WriteComm(0xCCb0); //ccb1[7:0] : reg setting for signal01 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCb1); //ccb2[7:0] : reg setting for signal02 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCb2); //ccb3[7:0] : reg setting for signal03 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCb3); //ccb4[7:0] : reg setting for signal04 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCb4); //ccb5[7:0] : reg setting for signal05 selection with d2u mode
SPI_WriteData(0x0D);
SPI_WriteComm(0xCCb5); //ccb6[7:0] : reg setting for signal06 selection with d2u mode
SPI_WriteData(0x0F);
SPI_WriteComm(0xCCb6); //ccb7[7:0] : reg setting for signal07 selection with d2u mode
SPI_WriteData(0x09);
SPI_WriteComm(0xCCb7); //ccb8[7:0] : reg setting for signal08 selection with d2u mode
SPI_WriteData(0x0B);
SPI_WriteComm(0xCCb8); //ccb9[7:0] : reg setting for signal09 selection with d2u mode
SPI_WriteData(0x02);
SPI_WriteComm(0xCCb9); //ccba[7:0] : reg setting for signal10 selection with d2u mode
SPI_WriteData(0x01);
// cccx
SPI_WriteComm(0xCCc0); //ccc1[7:0] : reg setting for signal11 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCc1); //ccc2[7:0] : reg setting for signal12 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCc2); //ccc3[7:0] : reg setting for signal13 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCc3); //ccc4[7:0] : reg setting for signal14 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCc4); //ccc5[7:0] : reg setting for signal15 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCc5); //ccc6[7:0] : reg setting for signal16 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCc6); //ccc7[7:0] : reg setting for signal17 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCc7); //ccc8[7:0] : reg setting for signal18 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCc8); //ccc9[7:0] : reg setting for signal19 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCc9); //ccca[7:0] : reg setting for signal20 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCca); //cccb[7:0] : reg setting for signal21 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCcb); //cccc[7:0] : reg setting for signal22 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCcc); //cccd[7:0] : reg setting for signal23 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCcd); //ccce[7:0] : reg setting for signal24 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCce); //cccf[7:0] : reg setting for signal25 selection with d2u mode
SPI_WriteData(0x0E);
// ccdx
SPI_WriteComm(0xCCd0); //ccd1[7:0] : reg setting for signal26 selection with d2u mode
SPI_WriteData(0x10);
SPI_WriteComm(0xCCd1); //ccd2[7:0] : reg setting for signal27 selection with d2u mode
SPI_WriteData(0x0A);
SPI_WriteComm(0xCCd2); //ccd3[7:0] : reg setting for signal28 selection with d2u mode
SPI_WriteData(0x0C);
SPI_WriteComm(0xCCd3); //ccd4[7:0] : reg setting for signal29 selection with d2u mode
SPI_WriteData(0x04);
SPI_WriteComm(0xCCd4); //ccd5[7:0] : reg setting for signal30 selection with d2u mode
SPI_WriteData(0x03);
SPI_WriteComm(0xCCd5); //ccd6[7:0] : reg setting for signal31 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCd6); //ccd7[7:0] : reg setting for signal32 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCd7); //ccd8[7:0] : reg setting for signal33 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCd8); //ccd9[7:0] : reg setting for signal34 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCd9); //ccda[7:0] : reg setting for signal35 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCda); //ccdb[7:0] : reg setting for signal36 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCdb); //ccdc[7:0] : reg setting for signal37 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCdc); //ccdd[7:0] : reg setting for signal38 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCdd); //ccde[7:0] : reg setting for signal39 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0xCCde); //ccdf[7:0] : reg setting for signal40 selection with d2u mode
SPI_WriteData(0x00);
SPI_WriteComm(0x3A77); // RGB 18bits D[17:0]
SPI_WriteData(0x77);
SPI_WriteComm(0x1100);
delay_ms(12);
SPI_WriteComm(0x2900);
delay_ms(5);
}
。。