请帮忙看看我ds18b20的verilog代码哪里有错，急

时间：10-02 整理：3721RD 点击：

复制代码

module ds18b20_control_module(
input clk,
input rst_n,
output [15:0]Temper,
output read_finish,
output [3:0]flag,
inout DQ,
input Start
);
reg [15:0]rTemper;
//DQ三态
reg rDQ;
reg isRead;
assign DQ = isRead?1'bz:rDQ;
//1us 定时和计数器
reg [5:0] time_1us_cnt;
reg isCount;
always @(posedge clk or negedge rst_n)
if(！rst_n)
time_1us_cnt <= 6'd0;
else if(time_1us_cnt == 6'd49)
time_1us_cnt <= 6'd0;
else if(isCount)
time_1us_cnt <= time_1us_cnt + 1'b1;
else if(！isCount)
time_1us_cnt <= 6'd0;
reg [10:0]time_cnt;
reg [10:0]Times;
always @(posedge clk or negedge rst_n)
if(！rst_n)
time_cnt <= 11'd0;
else if(time_cnt == Times)
time_cnt <= 11'd0;
else if(isCount && time_1us_cnt == 6'd49 )
time_cnt <= time_cnt + 1'b1;
else if(！isCount)
time_cnt <= 11'd0;
//1S定时器
reg [25:0]time_1s_cnt;
always @(posedge clk or negedge rst_n)
if(！rst_n)
time_1s_cnt <= 26'd0;
else if(time_1s_cnt == 26'd49_999_999)
time_1s_cnt <= 26'd0;
else if(isCount)
time_1s_cnt <= time_1s_cnt + 1'b1;
else if(！isCount)
time_1s_cnt <= 26'd0;
//状态机
reg [2:0]state;
reg ack;
reg flag_r;
parameter IDLE = 3'd0;
parameter RESET = 3'd1;
parameter RECEIVE = 3'd2;
parameter WRITE_ROM = 3'd3;
parameter WRITE_COMMAND_44 = 3'd4;
parameter WRITE_COMMAND_BE = 3'd5;
parameter WAIT = 3'd6;
parameter READ = 3'd7;
reg [3:0]bit_counter;
reg [3:0]i;
reg [3:0]j;
reg [7:0]command;
reg read_finish_r;
reg command_finish;
reg [15:0]ds18b20_read_data;
reg [3:0]rflag;
always @(posedge clk or negedge rst_n)
if(！rst_n)
begin
state <= 3'd0;
rTemper <= 16'd0;
isCount <= 1'b0;
rDQ <= 1'b1;
isRead <= 1'b0;
ack <= 1'b1;
command <= 8'd0;
flag_r <= 1'b0;
i <= 4'd0;
j <= 4'd0;
bit_counter <= 4'd0;
read_finish_r <= 1'b0;
command_finish <= 1'b0;
ds18b20_read_data <= 16'd0;
rflag <= 4'd0;
end
else
case(state)
IDLE:begin
if(Start) state <= RESET ;
end
//复位
RESET:begin
if(time_cnt == Times)begin
isCount <= 1'b0;
state <= RECEIVE;
end
else begin
isCount <= 1'b1;
isRead <= 1'b0;
rDQ <= 1'b0;
Times <= 600;
end
end
//接收
RECEIVE:begin
if(time_cnt == 70) begin ack <= DQ; end
else if(time_cnt == 600)begin
isCount <= 1'b0;
if(ack == 1'b0) begin
state <= WRITE_ROM;
end
else state <= IDLE ;
end
else begin
isCount <= 1'b1;
Times <= 600;
isRead <= 1'b1;
rDQ <= 1'b1;
end
end
//写cc指令
WRITE_ROM:begin
case(i)
0:
begin isRead <= 1'b0;isCount <= 1'b1;Times <= 11'd100; i <= i + 1'b1;command <= 8'hCC;end
1:
if(time_cnt == 5)begin i <= i +1'b1; end
else rDQ <= 1'b0;
2:
if(time_cnt == 90)i <= i +1'b1;
else rDQ <= command[bit_counter];
3:
if(time_cnt == 100) begin isCount <= 1'b0; i <= i + 1'b1; end
else begin isRead <= 1'b1;rDQ <= 1'b1;end
4:
if( bit_counter == 7)begin bit_counter <= 4'd0; i <= i + 1'b1; end
else begin bit_counter <= bit_counter + 1'b1; i <= 4'd0; end
5:
begin command_finish <= 1'b1;i <= i + 1'b1; end
6:
begin
if(flag_r == 1'b0)begin state <= WRITE_COMMAND_44;command_finish <= 1'b0; i <= 4'd0; end
else if( flag_r == 1'b1)begin state <= WRITE_COMMAND_BE;command_finish <= 1'b0; i <= 4'd0;end
end
endcase
end
//写44转换
WRITE_COMMAND_44:begin
case(i)
0:
begin isRead <= 1'b0;isCount <= 1'b1;Times <= 11'd100; i <= i + 1'b1;command <= 8'h44;end
1:
if(time_cnt == 5)begin i <= i +1'b1; end
else rDQ <= 1'b0;
2:
if(time_cnt == 90)i <= i +1'b1;
else rDQ <= command[bit_counter];
3:
if(time_cnt == 100) begin isCount <= 1'b0; i <= i + 1'b1; end
else isRead <= 1'b1;// rDQ <= 1'b1;
4:
if( bit_counter == 7)begin bit_counter <= 4'd0; i <= i + 1'b1; end
else begin bit_counter <= bit_counter + 1'b1; i <= 4'd0; end
5:
begin command_finish <= 1'b1;i <= i + 1'b1; end
6:
begin command_finish <= 1'b0; state <= WAIT ; i <= 4'd0;end
endcase
end
WRITE_COMMAND_BE:begin
case(i)
0:
begin isRead <= 1'b0;isCount <= 1'b1;Times <= 11'd100; i <= i + 1'b1;command <= 8'hBE;end
1:
if(time_cnt == 5)begin i <= i +1'b1; end
else rDQ <= 1'b0;
2:
if(time_cnt == 90)i <= i +1'b1;
else rDQ <= command[bit_counter];
3:
if(time_cnt == 100) begin isCount <= 1'b0; i <= i + 1'b1; end
else isRead <= 1'b1;//rDQ <= 1'b1;
4:
if( bit_counter == 7)begin bit_counter <= 4'd0; i <= i + 1'b1; end
else begin bit_counter <= bit_counter + 1'b1; i <= 4'd0; end
5:
begin command_finish <= 1'b1;i <= i + 1'b1; end
6:
begin command_finish <= 1'b0; state <= READ ; i <= 4'd0; end
endcase
end
//等待1s
WAIT:begin
if(time_1s_cnt == 26'd42_999_999)begin state <=RESET;flag_r <= 1'b1;isCount <= 1'b0; end
else begin isCount <= 1'b1; end
end
//读取
READ:begin
case(j)
0:
begin isCount <= 1'b1;Times <= 11'd100; j <= j + 1'b1;flag_r <= 1'b0;end
1:
if(time_cnt == 3) j <= j +1'b1;
else begin isRead <= 1'b0;rDQ <= 1'b0;end
2:
if(time_cnt == 80) j <= j +1'b1;
else if(time_cnt == 10)begin ds18b20_read_data <= {DQ,ds18b20_read_data[15:1]}; end
else begin isRead <= 1'b1;rDQ <= 1'b1;end
3:
if(time_cnt == 90) begin isCount <= 1'b0; j <= j + 1'b1; end
else begin end//isRead <= 1'b0;rDQ <= 1'b1;end
4:
if( bit_counter == 15)begin bit_counter <= 4'd0; j <= j + 1'b1; end
else begin bit_counter <= bit_counter + 1'b1; j <= 4'd0; end
5:
begin read_finish_r <= 1'b1;j <= j + 1'b1; end
6:
begin
state <= IDLE ; read_finish_r <= 1'b0;rTemper <= ds18b20_read_data ;rflag[0]<=1;
end
endcase
end
endcase
assign Temper = rTemper ;
assign read_finish = read_finish_r;
assign flag = rflag;
endmodule

复制代码

module ds18b20_control_module(
input clk,
input rst_n,
output [15:0]Temper,
output read_finish,
output [3:0]flag,
inout DQ,
input Start
);
reg [15:0]rTemper;
//DQ三态
reg rDQ;
reg isRead;
assign DQ = isRead?1'bz:rDQ;
//1us 定时和计数器
reg [5:0] time_1us_cnt;
reg isCount;
always @(posedge clk or negedge rst_n)
if(！rst_n)
time_1us_cnt <= 6'd0;
else if(time_1us_cnt == 6'd49)
time_1us_cnt <= 6'd0;
else if(isCount)
time_1us_cnt <= time_1us_cnt + 1'b1;
else if(！isCount)
time_1us_cnt <= 6'd0;
reg [10:0]time_cnt;
reg [10:0]Times;
always @(posedge clk or negedge rst_n)
if(！rst_n)
time_cnt <= 11'd0;
else if(time_cnt == Times)
time_cnt <= 11'd0;
else if(isCount && time_1us_cnt == 6'd49 )
time_cnt <= time_cnt + 1'b1;
else if(！isCount)
time_cnt <= 11'd0;
//1S定时器
reg [25:0]time_1s_cnt;
always @(posedge clk or negedge rst_n)
if(！rst_n)
time_1s_cnt <= 26'd0;
else if(time_1s_cnt == 26'd49_999_999)
time_1s_cnt <= 26'd0;
else if(isCount)
time_1s_cnt <= time_1s_cnt + 1'b1;
else if(！isCount)
time_1s_cnt <= 26'd0;
//状态机
reg [2:0]state;
reg ack;
reg flag_r;
parameter IDLE = 3'd0;
parameter RESET = 3'd1;
parameter RECEIVE = 3'd2;
parameter WRITE_ROM = 3'd3;
parameter WRITE_COMMAND_44 = 3'd4;
parameter WRITE_COMMAND_BE = 3'd5;
parameter WAIT = 3'd6;
parameter READ = 3'd7;
reg [3:0]bit_counter;
reg [3:0]i;
reg [3:0]j;
reg [7:0]command;
reg read_finish_r;
reg command_finish;
reg [15:0]ds18b20_read_data;
reg [3:0]rflag;
always @(posedge clk or negedge rst_n)
if(！rst_n)
begin
state <= 3'd0;
rTemper <= 16'd0;
isCount <= 1'b0;
rDQ <= 1'b1;
isRead <= 1'b0;
ack <= 1'b1;
command <= 8'd0;
flag_r <= 1'b0;
i <= 4'd0;
j <= 4'd0;
bit_counter <= 4'd0;
read_finish_r <= 1'b0;
command_finish <= 1'b0;
ds18b20_read_data <= 16'd0;
rflag <= 4'd0;
end
else
case(state)
IDLE:begin
if(Start) state <= RESET ;
end
//复位
RESET:begin
if(time_cnt == Times)begin
isCount <= 1'b0;
state <= RECEIVE;
end
else begin
isCount <= 1'b1;
isRead <= 1'b0;
rDQ <= 1'b0;
Times <= 600;
end
end
//接收
RECEIVE:begin
if(time_cnt == 70) begin ack <= DQ; end
else if(time_cnt == 600)begin
isCount <= 1'b0;
if(ack == 1'b0) begin
state <= WRITE_ROM;
end
else state <= IDLE ;
end
else begin
isCount <= 1'b1;
Times <= 600;
isRead <= 1'b1;
rDQ <= 1'b1;
end
end
//写cc指令
WRITE_ROM:begin
case(i)
0:
begin isRead <= 1'b0;isCount <= 1'b1;Times <= 11'd100; i <= i + 1'b1;command <= 8'hCC;end
1:
if(time_cnt == 5)begin i <= i +1'b1; end
else rDQ <= 1'b0;
2:
if(time_cnt == 90)i <= i +1'b1;
else rDQ <= command[bit_counter];
3:
if(time_cnt == 100) begin isCount <= 1'b0; i <= i + 1'b1; end
else begin isRead <= 1'b1;rDQ <= 1'b1;end
4:
if( bit_counter == 7)begin bit_counter <= 4'd0; i <= i + 1'b1; end
else begin bit_counter <= bit_counter + 1'b1; i <= 4'd0; end
5:
begin command_finish <= 1'b1;i <= i + 1'b1; end
6:
begin
if(flag_r == 1'b0)begin state <= WRITE_COMMAND_44;command_finish <= 1'b0; i <= 4'd0; end
else if( flag_r == 1'b1)begin state <= WRITE_COMMAND_BE;command_finish <= 1'b0; i <= 4'd0;end
end
endcase
end
//写44转换
WRITE_COMMAND_44:begin
case(i)
0:
begin isRead <= 1'b0;isCount <= 1'b1;Times <= 11'd100; i <= i + 1'b1;command <= 8'h44;end
1:
if(time_cnt == 5)begin i <= i +1'b1; end
else rDQ <= 1'b0;
2:
if(time_cnt == 90)i <= i +1'b1;
else rDQ <= command[bit_counter];
3:
if(time_cnt == 100) begin isCount <= 1'b0; i <= i + 1'b1; end
else isRead <= 1'b1;// rDQ <= 1'b1;
4:
if( bit_counter == 7)begin bit_counter <= 4'd0; i <= i + 1'b1; end
else begin bit_counter <= bit_counter + 1'b1; i <= 4'd0; end
5:
begin command_finish <= 1'b1;i <= i + 1'b1; end
6:
begin command_finish <= 1'b0; state <= WAIT ; i <= 4'd0;end
endcase
end
WRITE_COMMAND_BE:begin
case(i)
0:
begin isRead <= 1'b0;isCount <= 1'b1;Times <= 11'd100; i <= i + 1'b1;command <= 8'hBE;end
1:
if(time_cnt == 5)begin i <= i +1'b1; end
else rDQ <= 1'b0;
2:
&nbs

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