quartus调用modelsim仿真时出现Fatal error in Process line__12

VHDL代码：
library ieee;
use ieee.std_logic_1164.all;
entity mux is
        port(a,b,c,d,s0,s1:in std_logic;
                  y:out std_logic);
end mux;
architecture mux_arch of mux is
        signal sel:integer range 0 to 3;
begin
        process(a,b,c,d,s0,s1)
        begin
        sel y y y y <= d;
        end case;
        end process;
end mux_arch;
quartus和modelsim联调仿真时，modelsim中出现Fatal error in Process line__12 at E:/quartus project/mux41/mux.vhd line 17怎么解决，大神帮帮忙！