帮忙写一下ASK解调模块的测试文件,自己写的仿真不出来,谢谢,急急急!
时间:10-02
整理:3721RD
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解调模块
module Ask_two(clk,reset,x,y); input clk; input reset; input x; output y;
reg y;
reg[2:0]cnt; reg[2:0]m;
always@(posedge clk)begin
if(!reset)begin
cnt<=3'b000; end
else if(cnt==3'b111) cnt<=3'b000; else
cnt<=cnt+1; end
always@(posedge x)begin if(!reset)begin m<=3'b000; end
else begin
if(cnt==3'b110)begin if(m<=3'b010) y<=1'b0; else
y<=1'b1; m<=3'b000; end else
m<=m+1; end end
endmodule
module Ask_two(clk,reset,x,y); input clk; input reset; input x; output y;
reg y;
reg[2:0]cnt; reg[2:0]m;
always@(posedge clk)begin
if(!reset)begin
cnt<=3'b000; end
else if(cnt==3'b111) cnt<=3'b000; else
cnt<=cnt+1; end
always@(posedge x)begin if(!reset)begin m<=3'b000; end
else begin
if(cnt==3'b110)begin if(m<=3'b010) y<=1'b0; else
y<=1'b1; m<=3'b000; end else
m<=m+1; end end
endmodule
大神们,都来看看,求助!
这是我写的测试文件,仿真达不到想要的结果,没有看见解调的现象
`timescale 1ns/1ps
module OOK_de2_tb;
reg clk;
reg reset;
reg x;
wire y;
OOK_de2 u1(
.clk(clk),
.reset(reset),
.x(x),
.y(y)
);
always #5 clk = ~clk;
initial
begin
clk = 1'b0;
reset = 1'b0;
#10;
reset = 1'b1;
always @(posedge clk)
begin
x = 1'b1;
#5 x= 1'b0;
end
endmodule
走过路过的,都来看看,一起探讨一下,到底怎么回事,目的要看到解调的效果