用Quartus II 13.0 (64-bit) Web Edition做一个10进制的计数器,然后用led数码管显示,加一个1s的延时?
时间:10-02
整理:3721RD
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我已完成以下代码,不知延时怎么加!大神求帮助! 求大神帮助!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test4 is
port (clk,clr,en : in std_logic;
co : out std_logic;
dout : out std_logic_vector(3 downto 0);
m: out std_logic_vector(3 downto 0);
SEGOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
SELOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end test4;
architecture behav of test4 is
SIGNAL SEC : STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
process(clk,clr,en)
variable Q : std_logic_vector(3 downto 0);
begin
m '0');
elsif Q '0');
end if;
end if;
end if;
if Q="0000" then co SEGOUT SEGOUT SEGOUT SEGOUT SEGOUT SEGOUT SEGOUT SEGOUT SEGOUT SEGOUT NULL;
end CASE;
dout <= Q;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test4 is
port (clk,clr,en : in std_logic;
co : out std_logic;
dout : out std_logic_vector(3 downto 0);
m: out std_logic_vector(3 downto 0);
SEGOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
SELOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end test4;
architecture behav of test4 is
SIGNAL SEC : STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
process(clk,clr,en)
variable Q : std_logic_vector(3 downto 0);
begin
m '0');
elsif Q '0');
end if;
end if;
end if;
if Q="0000" then co SEGOUT SEGOUT SEGOUT SEGOUT SEGOUT SEGOUT SEGOUT SEGOUT SEGOUT SEGOUT NULL;
end CASE;
dout <= Q;
end process;
end behav;
根据时钟频率,做个counter卡1秒的时间,然后由这个1秒时间的信号去控制输出
