特权同学写的sram读写代码的状态机有必要吗?
时间:10-02
整理:3721RD
点击:
请问大家有没有看过特权同学的sram读写代码呀?为什么要设置状态机呢?感觉就是在整个状态机就是在等待延时啊?直接用计数器或者是延时模块不可以吗?
parameter IDLE = 4'd0,
WRT0 = 4'd1,
WRT1 = 4'd2,
REA0 = 4'd3,
REA1 = 4'd4;
reg[3:0] cstate,nstate;
always @ (posedge clk or negedge rst_n)
if(!rst_n) cstate <= IDLE;
else cstate <= nstate;
always @ (cstate or sram_wr_req or sram_rd_req or cnt)
case (cstate)
IDLE: if(sram_wr_req) nstate <= WRT0; //进入写状态
else if(sram_rd_req) nstate <= REA0; //进入读状态
else nstate <= IDLE;
WRT0: if(`DELAY_80NS) nstate <= WRT1;
else nstate <= WRT0; //延时等待160ns
WRT1: nstate <= IDLE; //写结束,返回
REA0: if(`DELAY_80NS) nstate <= REA1;
else nstate <= REA0; //延时等待160ns
REA1: nstate <= IDLE; //读结束,返回
default: nstate <= IDLE;
endcase
//-------------------------------------
assign sram_addr = addr_r; // SRAM地址总线连接
整个状态机和最后一句话有什么直接联系吗?求解谢谢
parameter IDLE = 4'd0,
WRT0 = 4'd1,
WRT1 = 4'd2,
REA0 = 4'd3,
REA1 = 4'd4;
reg[3:0] cstate,nstate;
always @ (posedge clk or negedge rst_n)
if(!rst_n) cstate <= IDLE;
else cstate <= nstate;
always @ (cstate or sram_wr_req or sram_rd_req or cnt)
case (cstate)
IDLE: if(sram_wr_req) nstate <= WRT0; //进入写状态
else if(sram_rd_req) nstate <= REA0; //进入读状态
else nstate <= IDLE;
WRT0: if(`DELAY_80NS) nstate <= WRT1;
else nstate <= WRT0; //延时等待160ns
WRT1: nstate <= IDLE; //写结束,返回
REA0: if(`DELAY_80NS) nstate <= REA1;
else nstate <= REA0; //延时等待160ns
REA1: nstate <= IDLE; //读结束,返回
default: nstate <= IDLE;
endcase
//-------------------------------------
assign sram_addr = addr_r; // SRAM地址总线连接
整个状态机和最后一句话有什么直接联系吗?求解谢谢