串入并出移位寄存器出现问题？
时间：10-02
整理：3721RD
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代码编译报错信息为process clocking is too complex，不知道代码哪儿错了，求高手指教！
- LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- ENTITY ser_to_para is
- PORT(serin,clk,st:IN STD_LOGIC;
- para:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
- END ENTITY ser_to_para;
- ARCHITECTURE behav of ser_to_para is
- BEGIN
- PROCESS(st,clk)
- VARIABLE temp:STD_LOGIC_VECTOR(7 DOWNTO 0);
- BEGIN
- IF(st='1')then
- IF rising_edge(clk) THEN
- FOR n IN 0 TO 7 LOOP
- temp(n):=serin;
- END LOOP; END IF;
- para<=temp;
- ELSE
- para<="ZZZZZZZZ";
- END IF;
- END PROCESS;
- END behav;