用ISE仿真怎么波形都是棕黄色直线啊,value都为U
时间:10-02
整理:3721RD
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用ISE仿真怎么波形都是棕黄色直线啊,value都为U,它们的初始值不是已经设为‘0’了吗?怎么还会出现这种情况,不太明白,下面是我的测试代码,设计的是:X=not(a and b),Y=not(not b and c and d)
测试代码如下:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY project_test IS
END project_test;
ARCHITECTURE behavior OF project_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT project
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
x : OUT std_logic;
y : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic := '0';
signal d : std_logic := '0';
--Outputs
signal x : std_logic;
signal y : std_logic;
-- No clocks detected in port list. Replace below with
-- appropriate port name
constant _period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: project PORT MAP (
a => a,
b => b,
c => c,
d => d,
x => x,
y => y
);
-- Clock process definitions
_process :process
begin
_period/2;
_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
a _period*10;
a<='0';b<='1';c<='0';d<='0';
-- insert stimulus here
wait;
end process;
END;
测试代码如下:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY project_test IS
END project_test;
ARCHITECTURE behavior OF project_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT project
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
x : OUT std_logic;
y : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic := '0';
signal d : std_logic := '0';
--Outputs
signal x : std_logic;
signal y : std_logic;
-- No clocks detected in port list. Replace below with
-- appropriate port name
constant _period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: project PORT MAP (
a => a,
b => b,
c => c,
d => d,
x => x,
y => y
);
-- Clock process definitions
_process :process
begin
_period/2;
_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
a _period*10;
a<='0';b<='1';c<='0';d<='0';
-- insert stimulus here
wait;
end process;
END;