新学用VHDL写时钟程序，不能同时显示4位数字

刚开始学，突然不太清楚数码管动态显示问题了，写的程序不能同时显示4位数码管，时间还是听精确的
晶振50M
LIBRARY IEEE;
        USE IEEE.STD_LOGIC_1164.ALL;
        USE IEEE.STD_LOGIC_ARITH.ALL;
        USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CLOCK1 IS
        PORT(CLK:IN STD_LOGIC;
                  DATAOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
                  EN_COM:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY;
ARCHITECTURE BEHAVIORAL OF CLOCK1 IS
        SIGNAL CLK1,CLK2:STD_LOGIC;
        SIGNAL DATA:STD_LOGIC_VECTOR(7 DOWNTO 0);
        signal EN:STD_LOGIC_VECTOR(3 DOWNTO 0);
        SIGNAL COUNTER:INTEGER RANGE 0 TO 9;
        signal counter1:integer range 0 to 9;
        signal counter2:integer range 0 to 5;
        signal counter3:integer range 0 to 9;
        signal counter4:integer range 0 to 5;       
        SIGNAL FIRST,SECOND,THIRD,LAST:STD_LOGIC:='0';
        SIGNAL SEG:STD_LOGIC_VECTOR(3 DOWNTO 0);
       
BEGIN
        DATAOUT en en en en en COUNTER COUNTER COUNTER COUNTER counter DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA <="00010000";
        END CASE;
        end process;
END BEHAVIORAL;
       

没事了，会了。位选扫描没写好

才女就是才女，一看就会