格雷码转换成8421码的VHDL设计，编译出错不会改，求好心人...

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY g2b IS
GENERIC(n:INTEGER:=4);
PORT(grey : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);
     norm : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0));
END g2b;
ARCHITECTURE behave OF g2b IS
SIGNAL temp_normal:STD_LOGIC_VECTOR(n-1 DOWNTO 0);
SIGNAL temp_grey:STD_LOGIC_VECTOR(n-1 DOWNTO 0);
BEGIN
PROCESS(grey)
BEGIN
temp_normal(n-1) <= temp_grey(n-1);
FOR i IN n-2 DOWNTO 0 LOOP
temp_normal(i) <= temp_normal(i+1) XOR temp_grey(i);
END LOOP;
norm<=temp_normal;
END PROCESS;
END behave;

看不懂这错，不会改啊

有没有好心人帮帮忙?

急用啊！要交哪！