modelsim激励程序怎么编写
时间：10-02
整理：3721RD
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这是pwm波的设计程序，如何编写modlesim激励程序，求大神指点，目前modelsim软件不会用啊
module PWM(clk,PWM_in,PWM_out);
input clk;
input[7:0]PWM_in;
output PWM_out;
reg[8:0]PWM_accumulator;
always@(posedge clk)PWM_accumulator<=PWM_accumulator[7:0]+PWM_in;
assign PWM_out=PWM_accumulator[8];
endmodule
module PWM(clk,PWM_in,PWM_out);
input clk;
input[7:0]PWM_in;
output PWM_out;
reg[8:0]PWM_accumulator;
always@(posedge clk)PWM_accumulator<=PWM_accumulator[7:0]+PWM_in;
assign PWM_out=PWM_accumulator[8];
endmodule
初学FPGA，同求！