FPGA 飓风二代 vhdl程序调试问题
时间:10-02
整理:3721RD
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datain接单片机P1口,sele接单片机P2口低四位,en接P2.4。下载到板子上调试的时候,发现分配给连接单片机的引脚灯正常,分配给输出引脚的灯没有变化?怎么回事,求解?谢谢。
代码如下:
--接受命令模块实体
LIBRARY ieee; --打开IEEE库
USE ieee.std_logic_1164.ALL; --打开STD_LOGIC_1164包集
USE ieee.std_logic_unsigned.ALL; --打开STD_LOGIC_unsigned包集
ENTITY Command_TxRx IS --定义实体
PORT (
Datain51: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
en : IN STD_LOGIC;
Sele: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
doutF: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
doutA: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ans: OUT STD_LOGIC:='1';
modesel:OUT STD_LOGIC;
waveform:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
trigernum:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
delaytime:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END Command_TxRx;
ARCHITECTURE bhv OF Command_TxRx IS
signal FTEMP:std_logic_vector(31 downto 0);
signal ATEMP:std_logic_vector(7 downto 0);
signal TRIGERTEMP:std_logic_vector(7 downto 0);
signal DELAYTEMP:std_logic_vector(7 downto 0);
signal enable:std_logic;
signal modeselect:std_logic;
signal waveselect:std_logic_vector(1 downto 0);
BEGIN
--COM1:
PROCESS(en,Sele)
BEGIN
IF en='1' THEN
CASE Sele IS
WHEN "0001" => modeselect waveselect(1 DOWNTO 0) FTEMP(7 DOWNTO 0) FTEMP(15 DOWNTO 8) FTEMP(23 DOWNTO 16) FTEMP(31 DOWNTO 24) ATEMP(7 DOWNTO 0) TRIGERTEMP(7 DOWNTO 0) DELAYTEMP(7 DOWNTO 0) enable
-- modeselect<=modeselect;
-- waveselect<=waveselect;
-- FTEMP<=FTEMP;
-- ATEMP<=ATEMP;
-- TRIGERTEMP<=TRIGERTEMP;
-- DELAYTEMP<=DELAYTEMP;
-- enable<=enable;
END CASE;
ELSE enable<='1';
END IF;
END PROCESS;
doutF<=FTEMP;
doutA<=ATEMP;
trigernum<=TRIGERTEMP;
delaytime<=DELAYTEMP;
ans<=enable;
modesel<=modeselect;
waveform<=waveselect;
END bhv;
代码如下:
--接受命令模块实体
LIBRARY ieee; --打开IEEE库
USE ieee.std_logic_1164.ALL; --打开STD_LOGIC_1164包集
USE ieee.std_logic_unsigned.ALL; --打开STD_LOGIC_unsigned包集
ENTITY Command_TxRx IS --定义实体
PORT (
Datain51: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
en : IN STD_LOGIC;
Sele: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
doutF: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
doutA: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ans: OUT STD_LOGIC:='1';
modesel:OUT STD_LOGIC;
waveform:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
trigernum:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
delaytime:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END Command_TxRx;
ARCHITECTURE bhv OF Command_TxRx IS
signal FTEMP:std_logic_vector(31 downto 0);
signal ATEMP:std_logic_vector(7 downto 0);
signal TRIGERTEMP:std_logic_vector(7 downto 0);
signal DELAYTEMP:std_logic_vector(7 downto 0);
signal enable:std_logic;
signal modeselect:std_logic;
signal waveselect:std_logic_vector(1 downto 0);
BEGIN
--COM1:
PROCESS(en,Sele)
BEGIN
IF en='1' THEN
CASE Sele IS
WHEN "0001" => modeselect waveselect(1 DOWNTO 0) FTEMP(7 DOWNTO 0) FTEMP(15 DOWNTO 8) FTEMP(23 DOWNTO 16) FTEMP(31 DOWNTO 24) ATEMP(7 DOWNTO 0) TRIGERTEMP(7 DOWNTO 0) DELAYTEMP(7 DOWNTO 0) enable
-- modeselect<=modeselect;
-- waveselect<=waveselect;
-- FTEMP<=FTEMP;
-- ATEMP<=ATEMP;
-- TRIGERTEMP<=TRIGERTEMP;
-- DELAYTEMP<=DELAYTEMP;
-- enable<=enable;
END CASE;
ELSE enable<='1';
END IF;
END PROCESS;
doutF<=FTEMP;
doutA<=ATEMP;
trigernum<=TRIGERTEMP;
delaytime<=DELAYTEMP;
ans<=enable;
modesel<=modeselect;
waveform<=waveselect;
END bhv;
先用软件自带的仿真工具分析下程序逻辑是否正确在到板子省调试