VCS 使用问题，无法打开verilog文件，求教
时间：10-02
整理：3721RD
点击：
错误提示如下：
Parsing design file 'Intro_Top.v'
Error-[V2KS] Verilog IEEE 1364-2000 syntax used
Intro_Top.v, 17
Verilog 2000 IEEE 1364-2000 syntax used : Ansi style port declaration.
Please compile with +v2k to support this construct.
Parsing design file 'TestBench.v'
Error-[SFCOR]
Source file cannot be opened
Source file "../../VCS/Extras.inc" cannot be opened for reading due to 'No
such file or directory'.
Please fix above issue and compile again.
"TestBench.v", 24
Source info: `include "../../VCS/Extras.inc"
我是在自己电脑上破解安装的，DC可以正常使用，但VCS启动时，命令vcs -RI xx.v xxx.v 之后就出现上述错误提示。
求教....
Parsing design file 'Intro_Top.v'
Error-[V2KS] Verilog IEEE 1364-2000 syntax used
Intro_Top.v, 17
Verilog 2000 IEEE 1364-2000 syntax used : Ansi style port declaration.
Please compile with +v2k to support this construct.
Parsing design file 'TestBench.v'
Error-[SFCOR]
Source file cannot be opened
Source file "../../VCS/Extras.inc" cannot be opened for reading due to 'No
such file or directory'.
Please fix above issue and compile again.
"TestBench.v", 24
Source info: `include "../../VCS/Extras.inc"
我是在自己电脑上破解安装的，DC可以正常使用，但VCS启动时，命令vcs -RI xx.v xxx.v 之后就出现上述错误提示。
求教....