DSP SCI 发送和接收触发问题
时间:10-02
整理:3721RD
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请问一下 DSP SCI 发送和接收是怎么触发的 我看例程里边也没有发送定时起什么的不知道怎么触发 请大神帮忙分析分析
// Step 5. User specific code, enable interrupts:
// Init send data. After each transmission this data
// will be updated for the next transmission
for(i = 0; i<2; i++)
{
sdataA[i] = i;
}
rdata_pointA = sdataA[0];
// Enable interrupts required for this example
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, INT1
PieCtrlRegs.PIEIER9.bit.INTx2=1; // PIE Group 9, INT2
IER = 0x100; // Enable CPU INT
EINT;
// Step 6. IDLE loop. Just sit and loop forever (optional):
for(;;);
}
void error(void)
{
asm(" ESTOP0"); // Test failed! Stop!
for (;;);
}
interrupt void sciaTxFifoIsr(void)
{
Uint16 i;
for(i=0; i< 2; i++)
{
SciaRegs.SCITXBUF=sdataA[i]; // Send data
}
for(i=0; i< 2; i++) //Increment send data for next cycle
{
sdataA[i] = (sdataA[i]+1) & 0x00FF;
}
SciaRegs.SCIFFTX.bit.TXFFINTCLR=1; // Clear SCI Interrupt flag
PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ACK
}
interrupt void sciaRxFifoIsr(void)
{
Uint16 i;
for(i=0;i<2;i++)
{
rdataA[i]=SciaRegs.SCIRXBUF.all; // Read data
}
for(i=0;i<2;i++) // Check received data
{
if(rdataA[i] != ( (rdata_pointA+i) & 0x00FF) ) error();
}
rdata_pointA = (rdata_pointA+1) & 0x00FF;
SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag
SciaRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag
PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ack
}
void scia_fifo_init()
{
SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback
// No parity,8 char bits,
// async mode, idle-line protocol
SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK,
// Disable RX ERR, SLEEP, TXWAKE
SciaRegs.SCICTL2.bit.TXINTENA =1;
SciaRegs.SCICTL2.bit.RXBKINTENA =1;
SciaRegs.SCIHBAUD = 0x0000;
SciaRegs.SCILBAUD = SCI_PRD;
SciaRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back
SciaRegs.SCIFFTX.all=0xC022;
SciaRegs.SCIFFRX.all=0x0022;
SciaRegs.SCIFFCT.all=0x00;
SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset
SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1;
SciaRegs.SCIFFRX.bit.RXFIFORESET=1;
}
// Step 5. User specific code, enable interrupts:
// Init send data. After each transmission this data
// will be updated for the next transmission
for(i = 0; i<2; i++)
{
sdataA[i] = i;
}
rdata_pointA = sdataA[0];
// Enable interrupts required for this example
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, INT1
PieCtrlRegs.PIEIER9.bit.INTx2=1; // PIE Group 9, INT2
IER = 0x100; // Enable CPU INT
EINT;
// Step 6. IDLE loop. Just sit and loop forever (optional):
for(;;);
}
void error(void)
{
asm(" ESTOP0"); // Test failed! Stop!
for (;;);
}
interrupt void sciaTxFifoIsr(void)
{
Uint16 i;
for(i=0; i< 2; i++)
{
SciaRegs.SCITXBUF=sdataA[i]; // Send data
}
for(i=0; i< 2; i++) //Increment send data for next cycle
{
sdataA[i] = (sdataA[i]+1) & 0x00FF;
}
SciaRegs.SCIFFTX.bit.TXFFINTCLR=1; // Clear SCI Interrupt flag
PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ACK
}
interrupt void sciaRxFifoIsr(void)
{
Uint16 i;
for(i=0;i<2;i++)
{
rdataA[i]=SciaRegs.SCIRXBUF.all; // Read data
}
for(i=0;i<2;i++) // Check received data
{
if(rdataA[i] != ( (rdata_pointA+i) & 0x00FF) ) error();
}
rdata_pointA = (rdata_pointA+1) & 0x00FF;
SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag
SciaRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag
PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ack
}
void scia_fifo_init()
{
SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback
// No parity,8 char bits,
// async mode, idle-line protocol
SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK,
// Disable RX ERR, SLEEP, TXWAKE
SciaRegs.SCICTL2.bit.TXINTENA =1;
SciaRegs.SCICTL2.bit.RXBKINTENA =1;
SciaRegs.SCIHBAUD = 0x0000;
SciaRegs.SCILBAUD = SCI_PRD;
SciaRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back
SciaRegs.SCIFFTX.all=0xC022;
SciaRegs.SCIFFRX.all=0x0022;
SciaRegs.SCIFFCT.all=0x00;
SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset
SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1;
SciaRegs.SCIFFRX.bit.RXFIFORESET=1;
}
