SR. PHYSICAL DESIGN METHODOLOGY ENGINEER（上海）
时间：10-02
整理：3721RD
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NVIDIA Hiring~~！
机会难得！业内大侠们快来看看喽~~~
欢迎大家将中英文简历发送到邮箱lulin@nvidia.com，也可以通过论坛给我发短消息，或者加我的MSN lucylinxiyang@hotmail.com。本人将定期更新NV最新招聘信息，欢迎长期关注。（本人就是NV的HR,所有岗位都非猎头哦~）
SR. PHYSICAL DESIGN METHODOLOGY ENGINEER
Job Description:
Responsible for the development of the physical design methodologies and flow automation for large and high speed semicustom chips using deep submicron processes. This includes evaluating and helping improve third party tools, developing internal tools and solutions, and supporting the physical design implementation team.
Requirements:
- BSEE or BSCS
- 3+ years of experience in large VLSI physical design implementation and automation and methodology.
- Strong experience in programming of one of the following area: C/C++, Perl, Python.
- Prior experience in timing closure, CTS, power distribution and analysis, power efficiency, RC extraction and correlation, xtalk analysis, signal EM, place and route, DRC/LVS and tapeout issues.
- Working knowledge of deep sub-micron issues.
- Should be a power user of P&R and timing analysis CAD tools from Magma (Blast, Talus), Synopsys (ICC/DC/PT/STAR-RC/Astro/PC), Cadence (SOCE), Mentor Graphics (Pinnacle/Olympus) or Atoptech.
- Proficiency using Perl, TCL, Make scripting.
- Knowledge/Proficiency of C/C++ or any other software language is a plus.
- Experience at 40nm and 28nm is a plus.
- Circuit level comprehension of time critical paths and Spice experience are a plus.
机会难得！业内大侠们快来看看喽~~~
欢迎大家将中英文简历发送到邮箱lulin@nvidia.com，也可以通过论坛给我发短消息，或者加我的MSN lucylinxiyang@hotmail.com。本人将定期更新NV最新招聘信息，欢迎长期关注。（本人就是NV的HR,所有岗位都非猎头哦~）
SR. PHYSICAL DESIGN METHODOLOGY ENGINEER
Job Description:
Responsible for the development of the physical design methodologies and flow automation for large and high speed semicustom chips using deep submicron processes. This includes evaluating and helping improve third party tools, developing internal tools and solutions, and supporting the physical design implementation team.
Requirements:
- BSEE or BSCS
- 3+ years of experience in large VLSI physical design implementation and automation and methodology.
- Strong experience in programming of one of the following area: C/C++, Perl, Python.
- Prior experience in timing closure, CTS, power distribution and analysis, power efficiency, RC extraction and correlation, xtalk analysis, signal EM, place and route, DRC/LVS and tapeout issues.
- Working knowledge of deep sub-micron issues.
- Should be a power user of P&R and timing analysis CAD tools from Magma (Blast, Talus), Synopsys (ICC/DC/PT/STAR-RC/Astro/PC), Cadence (SOCE), Mentor Graphics (Pinnacle/Olympus) or Atoptech.
- Proficiency using Perl, TCL, Make scripting.
- Knowledge/Proficiency of C/C++ or any other software language is a plus.
- Experience at 40nm and 28nm is a plus.
- Circuit level comprehension of time critical paths and Spice experience are a plus.