请教各位PADS高手帮忙感激不尽：在logic里更改原理图ECO到PCB时出错
时间：10-02
整理：3721RD
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各位高手大家好：我这里用pads logic更改了原理图，在通过pads layout link往pads layout里面ECO的过程中出错，下面是错误内容，麻烦帮忙看下，感激不尽，谢谢！
PADS Layout ECO Generator (Version 6.4v) 2013-3-7 15:15:13
Copyright (c) 2003 - 2008 Mentor Graphics Corp. - All rights reserved
Command line arguments: -e d:\PADS Projects\Logic.log -r p -a PART,NET -l PCB,NETCLASS,NET
ERROR: Wrong gate pin data at the line: G 0 93
18 msec
PADS Layout ECO Generator (Version 6.4v) 2013-3-7 15:15:13
Copyright (c) 2003 - 2008 Mentor Graphics Corp. - All rights reserved
Command line arguments: -e d:\PADS Projects\Logic.log -r p -a PART,NET -l PCB,NETCLASS,NET
ERROR: Wrong gate pin data at the line: G 0 93
18 msec
封装建的有问题