allegro 16.3从sigxpllorer设置好网络拓扑结构后更新到pcb出错
时间：10-02
整理：3721RD
点击：
现有DDR2的地址总线，在sigxplorer设置后T点之后更新到pcb中发现有一根地址总线add15没有加上T点，报警为红色，以下为更新工程的结果：请教高手原因?
Processing Net XM1ADDR15 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:42 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
*ERROR: There is no net in the Cset that has pins matching those in net# 0 in the Xnet.
Cset end point Group Buffer model Value net#
--------------------- ----- ----------------------------------- ----- ----
S5PC100==V1_0 U12.D18 IO S5PC100X8A_081223_pvhbsudtartg_t_00 NONE 0
S5PC100==V1_0 U4.L3 IO CDSDefaultIO_2p5v NONE 0
S5PC100==V1_0 U5.L3 IO CDSDefaultIO_2p5v NONE 0
S5PC100==V1_0 NET.T.1 rat-T NONE NONE 0
Xnet end point Group Buffer model Value net#
--------------------- ----- ----------------------------------- ----- ----
S5PC100==V1_0 U12.D18 IO S5PC100X8A_081223_pvhbsudtartg_t_00 NONE 0
*WARNING: Due to mapping error, Min Tree scheduling will be used for Net S5PC100==V1_0 XM1ADDR15.
Net S5PC100==V1_0 XM1ADDR15 Schedule: Default
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR14 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:42 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- --------------------------- ------------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G13 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.L2 Approximate Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.L2 Approximate Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR14.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR14.T.1->S5PC100==V1_0 U4.L2
S5PC100==V1_0 XM1ADDR14.T.1->S5PC100==V1_0 U5.L2
S5PC100==V1_0 U12.G13->S5PC100==V1_0 XM1ADDR14.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR12 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:42 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- --------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G12 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.R2 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.R2 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR12.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR12.T.1->S5PC100==V1_0 U4.R2
S5PC100==V1_0 XM1ADDR12.T.1->S5PC100==V1_0 U5.R2
S5PC100==V1_0 U12.G12->S5PC100==V1_0 XM1ADDR12.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR11 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:42 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- --------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.H11 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.P7 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.P7 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR11.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR11.T.1->S5PC100==V1_0 U4.P7
S5PC100==V1_0 XM1ADDR11.T.1->S5PC100==V1_0 U5.P7
S5PC100==V1_0 U12.H11->S5PC100==V1_0 XM1ADDR11.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR10 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:42 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- --------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G16 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.M2 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.M2 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR10.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR10.T.1->S5PC100==V1_0 U4.M2
S5PC100==V1_0 XM1ADDR10.T.1->S5PC100==V1_0 U5.M2
S5PC100==V1_0 U12.G16->S5PC100==V1_0 XM1ADDR10.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR9 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:42 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.B16 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.P3 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.P3 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR9.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR9.T.1->S5PC100==V1_0 U4.P3
S5PC100==V1_0 XM1ADDR9.T.1->S5PC100==V1_0 U5.P3
S5PC100==V1_0 U12.B16->S5PC100==V1_0 XM1ADDR9.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR8 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:42 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.A19 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.P8 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.P8 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR8.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR8.T.1->S5PC100==V1_0 U4.P8
S5PC100==V1_0 XM1ADDR8.T.1->S5PC100==V1_0 U5.P8
S5PC100==V1_0 U12.A19->S5PC100==V1_0 XM1ADDR8.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR7 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:42 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.B17 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.P2 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.P2 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR7.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR7.T.1->S5PC100==V1_0 U4.P2
S5PC100==V1_0 XM1ADDR7.T.1->S5PC100==V1_0 U5.P2
S5PC100==V1_0 U12.B17->S5PC100==V1_0 XM1ADDR7.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR6 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:42 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G11 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.N7 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.N7 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR6.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR6.T.1->S5PC100==V1_0 U4.N7
S5PC100==V1_0 XM1ADDR6.T.1->S5PC100==V1_0 U5.N7
S5PC100==V1_0 U12.G11->S5PC100==V1_0 XM1ADDR6.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR5 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:43 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.B15 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.N3 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.N3 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR5.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR5.T.1->S5PC100==V1_0 U4.N3
S5PC100==V1_0 XM1ADDR5.T.1->S5PC100==V1_0 U5.N3
S5PC100==V1_0 U12.B15->S5PC100==V1_0 XM1ADDR5.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR4 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:43 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.A17 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.N8 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.N8 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR4.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR4.T.1->S5PC100==V1_0 U4.N8
S5PC100==V1_0 XM1ADDR4.T.1->S5PC100==V1_0 U5.N8
S5PC100==V1_0 U12.A17->S5PC100==V1_0 XM1ADDR4.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR3 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:43 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.B20 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.N2 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.N2 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR3.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR3.T.1->S5PC100==V1_0 U4.N2
S5PC100==V1_0 XM1ADDR3.T.1->S5PC100==V1_0 U5.N2
S5PC100==V1_0 U12.B20->S5PC100==V1_0 XM1ADDR3.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR2 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:43 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.C23 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.M7 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.M7 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR2.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR2.T.1->S5PC100==V1_0 U4.M7
S5PC100==V1_0 XM1ADDR2.T.1->S5PC100==V1_0 U5.M7
S5PC100==V1_0 U12.C23->S5PC100==V1_0 XM1ADDR2.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR1 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:43 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.C19 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.M3 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.M3 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR1.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR1.T.1->S5PC100==V1_0 U4.M3
S5PC100==V1_0 XM1ADDR1.T.1->S5PC100==V1_0 U5.M3
S5PC100==V1_0 U12.C19->S5PC100==V1_0 XM1ADDR1.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR0 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:43 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G14 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.M8 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.M8 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR0.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR0.T.1->S5PC100==V1_0 U4.M8
S5PC100==V1_0 XM1ADDR0.T.1->S5PC100==V1_0 U5.M8
S5PC100==V1_0 U12.G14->S5PC100==V1_0 XM1ADDR0.T.1
Verify Schedule: VERIFY
Processing Net XM1ADDR15 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:42 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
*ERROR: There is no net in the Cset that has pins matching those in net# 0 in the Xnet.
Cset end point Group Buffer model Value net#
--------------------- ----- ----------------------------------- ----- ----
S5PC100==V1_0 U12.D18 IO S5PC100X8A_081223_pvhbsudtartg_t_00 NONE 0
S5PC100==V1_0 U4.L3 IO CDSDefaultIO_2p5v NONE 0
S5PC100==V1_0 U5.L3 IO CDSDefaultIO_2p5v NONE 0
S5PC100==V1_0 NET.T.1 rat-T NONE NONE 0
Xnet end point Group Buffer model Value net#
--------------------- ----- ----------------------------------- ----- ----
S5PC100==V1_0 U12.D18 IO S5PC100X8A_081223_pvhbsudtartg_t_00 NONE 0
*WARNING: Due to mapping error, Min Tree scheduling will be used for Net S5PC100==V1_0 XM1ADDR15.
Net S5PC100==V1_0 XM1ADDR15 Schedule: Default
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR14 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:42 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- --------------------------- ------------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G13 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.L2 Approximate Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.L2 Approximate Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR14.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR14.T.1->S5PC100==V1_0 U4.L2
S5PC100==V1_0 XM1ADDR14.T.1->S5PC100==V1_0 U5.L2
S5PC100==V1_0 U12.G13->S5PC100==V1_0 XM1ADDR14.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR12 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:42 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- --------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G12 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.R2 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.R2 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR12.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR12.T.1->S5PC100==V1_0 U4.R2
S5PC100==V1_0 XM1ADDR12.T.1->S5PC100==V1_0 U5.R2
S5PC100==V1_0 U12.G12->S5PC100==V1_0 XM1ADDR12.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR11 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:42 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- --------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.H11 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.P7 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.P7 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR11.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR11.T.1->S5PC100==V1_0 U4.P7
S5PC100==V1_0 XM1ADDR11.T.1->S5PC100==V1_0 U5.P7
S5PC100==V1_0 U12.H11->S5PC100==V1_0 XM1ADDR11.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR10 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:42 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- --------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G16 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.M2 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.M2 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR10.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR10.T.1->S5PC100==V1_0 U4.M2
S5PC100==V1_0 XM1ADDR10.T.1->S5PC100==V1_0 U5.M2
S5PC100==V1_0 U12.G16->S5PC100==V1_0 XM1ADDR10.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR9 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:42 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.B16 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.P3 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.P3 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR9.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR9.T.1->S5PC100==V1_0 U4.P3
S5PC100==V1_0 XM1ADDR9.T.1->S5PC100==V1_0 U5.P3
S5PC100==V1_0 U12.B16->S5PC100==V1_0 XM1ADDR9.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR8 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:42 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.A19 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.P8 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.P8 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR8.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR8.T.1->S5PC100==V1_0 U4.P8
S5PC100==V1_0 XM1ADDR8.T.1->S5PC100==V1_0 U5.P8
S5PC100==V1_0 U12.A19->S5PC100==V1_0 XM1ADDR8.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR7 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:42 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.B17 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.P2 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.P2 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR7.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR7.T.1->S5PC100==V1_0 U4.P2
S5PC100==V1_0 XM1ADDR7.T.1->S5PC100==V1_0 U5.P2
S5PC100==V1_0 U12.B17->S5PC100==V1_0 XM1ADDR7.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR6 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:42 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G11 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.N7 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.N7 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR6.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR6.T.1->S5PC100==V1_0 U4.N7
S5PC100==V1_0 XM1ADDR6.T.1->S5PC100==V1_0 U5.N7
S5PC100==V1_0 U12.G11->S5PC100==V1_0 XM1ADDR6.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR5 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:43 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.B15 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.N3 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.N3 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR5.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR5.T.1->S5PC100==V1_0 U4.N3
S5PC100==V1_0 XM1ADDR5.T.1->S5PC100==V1_0 U5.N3
S5PC100==V1_0 U12.B15->S5PC100==V1_0 XM1ADDR5.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR4 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:43 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.A17 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.N8 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.N8 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR4.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR4.T.1->S5PC100==V1_0 U4.N8
S5PC100==V1_0 XM1ADDR4.T.1->S5PC100==V1_0 U5.N8
S5PC100==V1_0 U12.A17->S5PC100==V1_0 XM1ADDR4.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR3 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:43 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.B20 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.N2 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.N2 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR3.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR3.T.1->S5PC100==V1_0 U4.N2
S5PC100==V1_0 XM1ADDR3.T.1->S5PC100==V1_0 U5.N2
S5PC100==V1_0 U12.B20->S5PC100==V1_0 XM1ADDR3.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR2 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:43 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.C23 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.M7 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.M7 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR2.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR2.T.1->S5PC100==V1_0 U4.M7
S5PC100==V1_0 XM1ADDR2.T.1->S5PC100==V1_0 U5.M7
S5PC100==V1_0 U12.C23->S5PC100==V1_0 XM1ADDR2.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR1 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:43 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.C19 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.M3 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.M3 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR1.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR1.T.1->S5PC100==V1_0 U4.M3
S5PC100==V1_0 XM1ADDR1.T.1->S5PC100==V1_0 U5.M3
S5PC100==V1_0 U12.C19->S5PC100==V1_0 XM1ADDR1.T.1
Verify Schedule: VERIFY
**************************************************************************
Processing Net XM1ADDR0 in design S5PC100==V1_0
Date/Time: Wed Oct 24 18:54:43 2012
Mapping Pins of Cset: DDR2_ADD_BUS
Mapping Mode: Pinuse and Refdes
Cset end point Xnet end point mapping mode
--------------------- -------------------------- ----------------
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G14 Refdes
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.M8 Refdes
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.M8 Refdes
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR0.T.1 Floating T-Point
Net Schedule: Template Defined
S5PC100==V1_0 XM1ADDR0.T.1->S5PC100==V1_0 U4.M8
S5PC100==V1_0 XM1ADDR0.T.1->S5PC100==V1_0 U5.M8
S5PC100==V1_0 U12.G14->S5PC100==V1_0 XM1ADDR0.T.1
Verify Schedule: VERIFY
发现先创建总线，然后手动在add15这根地址线上放置T点，然后创建ECset后，将地址总线的其它地址线也设置成相同的ECset后进入sigxplorer后在更新到PCB居然是可以的，但如果同样的过程只是不是在add15上手动放置T点，还是不行！是不是DDR的IBIS模型有问题?