如何写时钟模块才比较规范合理，大侠给个标准模板吧

如何写时钟模块才比较规范合理，大侠给个标准模板吧
`timescale 10ns / 1ns
module clktest(
clk,
reset,
datain,
dataout);
input clk;
input reset;
input [3:0]datain;
output[3:0]dataout;
wire clk;
wire reset;
wire clkout1;
wire clkout2;
wire clkout11;
wire clkout22;
clkgen clkgen(clk,reset,clkout1,clkout2);
datain_dataout datain_dataout(clkout1,clkout2,reset,datain,dataout);
endmodule
/////////////////////////////////////////////////////////////////
module clkgen(clk,reset,clkout1,clkout2);
input clk;
input reset;
output clkout1;
output clkout2;  
reg [3:0]cnt;
reg clkout11;
reg clkout22;
assign clkout1=！clkout11;
assign clkout2=！clkout22;

always @(posedge clk)begin
   if(！reset)
    cnt<=0;
   else
    cnt<=cnt+1;
  end
always @(posedge clk)
  begin  
   clkout11=~cnt[2];
   clkout22=~cnt[3];
   end
endmodule
////////////////////////////////////////////////////////
module datain_dataout(clkout1,clkout2,reset,datain,dataout);
input clkout1;
input clkout2;
input reset;
input [3:0]datain;
output [3:0]dataout;
reg [3:0]datatemp;
reg [3:0]dataout;
reg [3:0]cntt;
always @(posedge clkout2)begin
   if(！reset)
    cntt<=0;
   else
    cntt<=cntt+1;
  end

always @(posedge clkout1)begin
   if(！reset)
    datatemp<=0;
   else
    datatemp<=datain;
  end
always @(posedge clkout1)begin
   if(！reset)
    dataout<=0;
   else
    dataout<=datatemp;
  end

endmodule
////////////////////////////////////////////////
提示下面的警告：
clkgen.v(14): clock signal should not be driven (gated) by inverted logic (clock: "clkout1" (datain_dataout.v(28)); inverted logic output: "clkout1")

clkgen.v(14): clock signal should not be driven by logic which is not in clock_gen module (clock: "clkout1" (datain_dataout.v(22)); driving logic output: "clkout1")
clkgen.v(25): BLOCKING assignment should not be used in an edge triggered block