基于FPGA的单稳态脉冲展宽电路的设计问题！

请各位高手看看本人的程序，编译通过了，仿真却没有结果。我想实现的功能是单稳态脉冲展宽（通过外端口控制展宽宽度）。程序如下：
计数器（控制展宽电路的宽度）部分：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
  port(reset,en,clk: in std_logic;
       N1,N2,N3,N4: in std_logic;
       feed_out: out std_logic);
  end counter;
architecture Behavioral of counter is
signal temp: integer range 0 to 15:=0;
signal k:integer:=0;
begin
process(N1,N2,N3,N4,k,clk) is
begin
   if(N1='1') then temp<=temp+1;
  elsif(N2='1') then temp<=temp+2;
  elsif(N3='1') then temp<=temp+4;
  elsif(N4='1') then temp<=temp+8;
  else null;
  end if;
  if (clk'event and clk='1') then
    if (reset='1') then
       k<=0;
     feed_out<='0';
     elsif (en='1') then   
    if (k=temp-1) then
         feed_out<='1';
         k<=temp-1;
     else k<=k+1;
    end if;
    end if;
end if;
end process;
end Behavioral;
D触发器（脉冲前沿产生电路，又是展宽脉冲宽度形成电路）：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity D_trigger is
  port(D,clear: in std_logic;
       clk: in std_logic;
   Q: out std_logic);
end D_trigger;
architecture Behavioral of D_trigger is
begin
process(D,clear,clk) is
begin
  if (clear='1') then
    Q<='0';     
  elsif (clk'event and clk='1') then
    Q<=D;
  end if;
end process;  
end Behavioral;
外部综合部分：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pulse_expand is
  port(pulse_in,D_in: in std_logic;
       clk_in: in std_logic;
   n1,n2,n3,n4: in std_logic;
   pulsewidth_out: out std_logic);
end pulse_expand;
architecture Behavioral of pulse_expand is
signal a1,a2,a3: std_logic;
component counter is
   port(reset,en,clk: in std_logic;
      N1,N2,N3,N4: in std_logic;
        feed_out: out std_logic);
  end component counter;
  component  D_trigger is
     port(D,clear: in std_logic;
          clk: in std_logic;
      Q: out std_logic);
  end component D_trigger;
begin
P1: D_trigger port map (D=>D_in,clear=>a1,clk=>pulse_in,Q=>a2);
a3<= not a2;
P2: counter port map ( reset=>a3,en=>a2,clk=>clk_in,feed_out=>a1,
    N1=>n1,N2=>n2,N3=>n3,N4=>n4);
pulsewidth_out<=a2;
end Behavioral;
[ 本帖最后由 marshal403006 于 2008-6-2 09:38 编辑 ]