TQ2440启动代码分析（二）

be valid if the current mode is not SVC mode.

LTORG

这段程序的开始使用DATA 伪操作指明SMRDATA 标号处作为一段数据，而非代码。

接下来就用DCD 分配一个字的内存单元，一共13 个字数据。

SMRDATA DATA

; Memory configuration should be optimized for best performance

; The following parameter is not optimized.

; Memory access cycle parameter strategy

; 1) The memory settings is safe parameters even at HCLK=75Mhz.

; 2) SDRAM refresh period is for HCLK<=75Mhz.

DCD (0+(B1_BWSCON<4)+(B2_BWSCON<8)+(B3_BWSCON<12)+(B4_BWSCON<16)+(B5_BWSCON<20)+(B6_BWSCON<24)+(B7_BWSCON<28))

DCD ((B0_Tacs<13)+(B0_Tcos<11)+(B0_Tacc<8)+(B0_Tcoh<6)+(B0_Tah<4)+(B0_Tacp<2)+(B0_PMC)) ;GCS0

DCD ((B1_Tacs<13)+(B1_Tcos<11)+(B1_Tacc<8)+(B1_Tcoh<6)+(B1_Tah<4)+(B1_Tacp<2)+(B1_PMC)) ;GCS1

DCD ((B2_Tacs<13)+(B2_Tcos<11)+(B2_Tacc<8)+(B2_Tcoh<6)+(B2_Tah<4)+(B2_Tacp<2)+(B2_PMC)) ;GCS2

DCD ((B3_Tacs<13)+(B3_Tcos<11)+(B3_Tacc<8)+(B3_Tcoh<6)+(B3_Tah<4)+(B3_Tacp<2)+(B3_PMC)) ;GCS3

DCD ((B4_Tacs<13)+(B4_Tcos<11)+(B4_Tacc<8)+(B4_Tcoh<6)+(B4_Tah<4)+(B4_Tacp<2)+(B4_PMC)) ;GCS4

DCD ((B5_Tacs<13)+(B5_Tcos<11)+(B5_Tacc<8)+(B5_Tcoh<6)+(B5_Tah<4)+(B5_Tacp<2)+(B5_PMC)) ;GCS5

DCD ((B6_MT<15)+(B6_Trcd<2)+(B6_SCAN)) ;GCS6

DCD ((B7_MT<15)+(B7_Trcd<2)+(B7_SCAN)) ;GCS7

DCD ((REFEN<23)+(TREFMD<22)+(Trp<20)+(Tsrc<18)+(Tchr<16)+REFCNT)

DCD 0x32 ;SCLK power saving mode, BANKSIZE 128M/128M

DCD 0x30 ;MRSR6 CL=3clk

DCD 0x30 ;MRSR7 CL=3clk

BaseOfROM DCD |Image$$RO$$Base|

TopOfROM DCD |Image$$RO$$Limit|

BaseOfBSS DCD |Image$$RW$$Base|

BaseOfZero DCD |Image$$ZI$$Base|

EndOfBSS DCD |Image$$ZI$$Limit|

ALIGN

;Function for entering power down mode

; 1. SDRAM should be in self-refresh mode.

; 2. All interrupt should be maksked for SDRAM/DRAM self-refresh.

; 3. LCD controller should be disabled for SDRAM/DRAM self-refresh.

; 4. The I-cache may have to be turned on.

; 5. The location of the following code may have not to be changed.

;void EnterPWDN(int CLKCON);

EnterPWDN

mov r2,r0 ;r2=rCLKCON

tst r0,#0x8 ;SLEEP mode?

bne ENTER_SLEEP

ENTER_STOP

ldr r0,=REFRESH

ldr r3,[r0] ;r3=rREFRESH

mov r1, r3

orr r1, r1, #BIT_SELFREFRESH

str r1, [r0] ;Enable SDRAM self-refresh

mov r1,#16 ;wait until self-refresh is issued. may not be needed.

0 subs r1,r1,#1

bne %B0

ldr r0,=CLKCON ;enter STOP mode.

str r2,[r0]

mov r1,#32

0 subs r1,r1,#1 ;1) wait until the STOP mode is in effect.

bne %B0 ;2) Or wait here until the CPU&Peripherals will be turned-off

; Entering SLEEP mode, only the reset by wake-up is available.

ldr r0,=REFRESH ;exit from SDRAM self refresh mode.

str r3,[r0]

MOV_PC_LR

ENTER_SLEEP

;NOTE.

;1) rGSTATUS3 should have the return address after wake-up from SLEEP mode.

ldr r0,=REFRESH

ldr r1,[r0] ;r1=rREFRESH

orr r1, r1, #BIT_SELFREFRESH

str r1, [r0] ;Enable SDRAM self-refresh

mov r1,#16 ;Wait until self-refresh is issued,which may not be needed.

0 subs r1,r1,#1

bne %B0

ldr r1,=MISCCR

ldr r0,[r1]

orr r0,r0,#(7<17) ;Set SCLK0=0, SCLK1=0, SCKE=0.

str r0,[r1]

ldr r0,=CLKCON ; Enter sleep mode

str r2,[r0]

b . ;CPU will die here.

WAKEUP_SLEEP;从睡眠状态醒过来

;Release SCLKn after wake-up from the SLEEP mode.

ldr r1,=MISCCR

ldr r0,[r1]

bic r0,r0,#(7<17) ;SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:0->=SCKE.

str r0,[r1]

;Set memory control registers

ldr r0,=SMRDATA ;be careful!

ldr r1,=BWSCON ;BWSCON Address

add r2, r0, #52 ;End address of SMRDATA

0

ldr r3, [r0], #4

str r3, [r1], #4

cmp r2, r0

bne %B0

mov r1,#256

0 subs r1,r1,#1 ;1) wait until the SelfRefresh is released.

bne %B0

ldr r1,=GSTATUS3 ;GSTATUS3 has the start address just after SLEEP wake-up

ldr r0,[r1]

mov pc,r0

;=====================================================================

; Clock division test

; Assemble code, because VSYNC time is very short

;=====================================================================

EXPORT CLKdiv124

EXPORT CLKdiv144

CLKdiv124

ldr r0, = CLKdivN

ldr r1, = 0x3 ; 0x3 = 1:2:4

str r1, [r0]

; wait until clock is stable

nop

nop

nop

nop

nop

ldr r0, = REFRESH

ldr r1, [r0]

bic r1, r1, #0xff

bic r1, r1, #(0x7<8)

orr r1, r1, #0x470 ; REFCNT135

str r1, [r0]

nop

nop

nop

nop

nop

mov pc, lr

CLKdiv144

ldr r0, = CLKdivN

ldr r1, = 0x4 ; 0x4 = 1:4:4

str r1, [r0]

; wait until clock is stable

nop

nop

nop

nop

nop

ldr r0, = REFRESH

ldr r1, [r0]

bic r1, r1, #0xff

bic r1, r1, #(0x7<8)

orr r1, r1, #0x630 ; REFCNT675 - 1520

str r1, [r0]

nop

nop

nop

nop

nop

mov pc, lr

ALIGN;按照一定的规则对齐，^符号相当于伪指令MAP，用于定义一个结构化的内存表的