简单的JK触发器的VHDL程序

简单的JK触发器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY JKff_1 IS
PORT (J,K:IN STD_LOGIC;
clk : IN std_logic;
Q: out STD_LOGIC);
end JKff_1;
ARCHITECTURE behave OF JKff_1 IS
signal S:STD_LOGIC;
BEGIN
S<= (J and (not S)) or (S and (not K)) when clkevent and clk=0 ;
Q<=S ;
end behave;