异步与同步清零Verilog hdl表达程序

带异步清0、异步置1 的D 触发器
module DFF1(q,qn,d,clk,set,reset);
input d,clk,set,reset;
output q,qn;
reg q,qn;
always @(posedge clk or negedge set or negedge reset)
begin
if (!reset) begin
q <= 0; //异步清0，低电平有效
qn <= 1;
end
else if (!set) begin
q <= 1; //异步置1，低电平有效
qn <= 0;
end
else begin
q <= d;
qn <= ~d;
end
end
endmodule

带同步清0、同步置1 的D触发器
module DFF2(q,qn,d,clk,set,reset);
input d,clk,set,reset;
output q,qn;
reg q,qn;
always @(posedge clk)
begin
if (reset) begin
q <= 0; qn <= 1; //同步清0，高电平有效
end
else if (set) begin
q <=1; qn <=0; //同步置1，高电平有效
end
else begin
q <= d; qn <= ~d;
end
end
endmodule

异步清零：
always@(posedge clk or negedge rst )
begin
if(!rst) out <= 0;
else
begin ·················································
end
end

同步清零：
always@(posedgeclk)
begin
if(!rst) out <= 0;
else
begin ·················································
end
end