嵌入式linux学习笔记20160713-每天进步一点点，向嵌入式进军
时间：10-02
整理：3721RD
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看了很多ARM裸机硬件程序，感觉bootloader还没搞懂，根据2440的原文件精简了一下，不知道有没有错误?
GET option.inc
GET memcfg.inc
GET 2440addr.inc
ENTRY
b reset
reset:
;close watchdog
ldr r0,=WTCON
mov r1,0x0
str r1,[r0]
;disable interrupt
;ldr r0,=INTMSK
;ldr r1,=0x7fff
;str r1,[r0]
;ldr r0,=INTSUBMSK
;ldr r1,=0x7fff
;str r1,[r0]
mrs r0,cpsr
orr r0,r0,0xc0
msr cpsr,r0
;Adjust the LOCKTIME register
ldr r0,=LOCKTIME
ldr r1,=0xffffff
str r1,[r0]
;configure clock divide
ldr r0,=CLKdivN
mov r1,0x5
str r1,[r0]
;If HdivN is not 0, the CPU bus mode has to be changed from the fast bus mode to the asynchronous bus
;mode using following instructions.
mrc p15,0,r0,c1,c0,0
orr r0,r0,#0xc0000000
mcr p15,0,r0,c1,c0,0
;Configure UPLL
ldr r0,=UPLLCON
ldr r1,=((56<<12)+(2<<4)+2)
str r1,[r0]
nop ; Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.
nop
nop
nop
nop
nop
nop
;Configure MPLL
ldr r0,=MPLLCON
ldr r1,=((127<<12)+(2<<4)+1) ;Fin=12MHz
str r1,[r0]
;Set SDRAM control registers
;ldr r0,=SMRDATA
adrl r0, SMRDATA ;be careful！
ldr r1,=BWSCON ;BWSCON Address
add r2, r0, #52 ;End address of SMRDATA
0
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B0
;set the stack for C program
mov sp,#0x33000000
bl CopyProgramFromNand
bl Main
SMRDATA DATA
; Memory configuration should be optimized for best performance
; The following parameter is not optimized.
; Memory access cycle parameter strategy
; 1) The memory settings is safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK<=75Mhz.
DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
DCD 0x32 ;SCLK power saving mode, BANKSIZE 128M/128M
DCD 0x30 ;MRSR6 CL=3clk
DCD 0x30 ;MRSR7 CL=3clk
ALIGN
END
GET option.inc
GET memcfg.inc
GET 2440addr.inc
ENTRY
b reset
reset:
;close watchdog
ldr r0,=WTCON
mov r1,0x0
str r1,[r0]
;disable interrupt
;ldr r0,=INTMSK
;ldr r1,=0x7fff
;str r1,[r0]
;ldr r0,=INTSUBMSK
;ldr r1,=0x7fff
;str r1,[r0]
mrs r0,cpsr
orr r0,r0,0xc0
msr cpsr,r0
;Adjust the LOCKTIME register
ldr r0,=LOCKTIME
ldr r1,=0xffffff
str r1,[r0]
;configure clock divide
ldr r0,=CLKdivN
mov r1,0x5
str r1,[r0]
;If HdivN is not 0, the CPU bus mode has to be changed from the fast bus mode to the asynchronous bus
;mode using following instructions.
mrc p15,0,r0,c1,c0,0
orr r0,r0,#0xc0000000
mcr p15,0,r0,c1,c0,0
;Configure UPLL
ldr r0,=UPLLCON
ldr r1,=((56<<12)+(2<<4)+2)
str r1,[r0]
nop ; Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.
nop
nop
nop
nop
nop
nop
;Configure MPLL
ldr r0,=MPLLCON
ldr r1,=((127<<12)+(2<<4)+1) ;Fin=12MHz
str r1,[r0]
;Set SDRAM control registers
;ldr r0,=SMRDATA
adrl r0, SMRDATA ;be careful！
ldr r1,=BWSCON ;BWSCON Address
add r2, r0, #52 ;End address of SMRDATA
0
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B0
;set the stack for C program
mov sp,#0x33000000
bl CopyProgramFromNand
bl Main
SMRDATA DATA
; Memory configuration should be optimized for best performance
; The following parameter is not optimized.
; Memory access cycle parameter strategy
; 1) The memory settings is safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK<=75Mhz.
DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
DCD 0x32 ;SCLK power saving mode, BANKSIZE 128M/128M
DCD 0x30 ;MRSR6 CL=3clk
DCD 0x30 ;MRSR7 CL=3clk
ALIGN
END
好好学习天天向上