vhdl语言

如何用VHDL 语言实现右移位啊?求大神帮看看为什么实现不了右移位?
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity yiwei is
port(
clk:IN std_logic;
y:out std_logic_vector (7 downto 0) );
end yiwei;
architecture behave of yiwei is
signal q: std_logic_vector(7 downto 0);
begin
process(clk)
begin   
    if clk'event and clk='1' then
     q<="11110000";
     q(3 downto 0) <= q(7 downto 4);
    q(7 downto 4) <=(others=>q(7));
     end if;
     end process;
     y<=q;
     end behave;