Frequency dependant port (MWO)

Hi,

I'm modifying/improving a simple microwave oscillator. I have a device's S parameters (oscillator FET) and I'm constructing the rest of the circuit on the output (harmonic filters etc).

In MWO I would like a simulation setup where I have an source port that matches the S22 of the oscillator FET so I can design the circuit to match this.

I can set the usual 50ohm port to a static impedance, ie whatever the impedance at the fundamental is, and do my engineering, but then I also would like to see whats happening at the 2nd 3rd harmonics, and this requires a bit of tinkering, either three simulations in parallel or change the value by hand each time. What would be great is a simulator that swept through my S22 file and set the port impedance at each frequency as it swept through a frequency sweep to calculate the Sparams. I'd get to see the whole picture matched across the full frequency sweep.

I can't just use the Nport block for the FET as this would require me to model the full oscillator circuit, which is already constructed by ancient methods and no model exists. I kinda just want to use the FET's S22 as the port impedance source.

Is this possible? I'm using MWO, happy to hear about other simulators that might do something like this.

thanks

You cannot use S22 of the FET as Output S22 of the Oscillator because the feedback changes everything so S22 of the FET cannot be used instead.
A matching circuit is rarely needed and the output is generally connected 50 Ohm standard load impedance.But in case of delivering Optimum Power available from the Oscillator and if you need well suppressed harmonics' levels, a matching circuit ( that is also used filtering purpose) can be used.If you're able to do a "Load Pull Simulation for the Oscillator",you can see what'll happen if you change the Load Impedance before designing that matching circuit.The oscillator may reject to oscillate at some certain impedances but Load Pull Technique is very useful for Harmonic Suppression and Available Power.

Cheers for the reply BB.

So I can't really get away without modelling the complete oscillator cct and then doing a load pull... I was trying to avoid this as there's a dielectric puck in there and I'd rather avoid modelling that unless there was an equivalent way to model it without getting into 3D.

I suspect the output impedance of the FET at fundamental is 35 ohms (the width of track being used here seems to be critical and it calculates to this impedance), and was going to try and match to that.

Harmonic surpression is a vital thing I have to tackle. I have several microstrip filters in place but they are not doing it for me, and any artwork scratching just kills the output power. It all seems on a knife edge.

I'll have a head scratch and maybe start a new question when I get stuck again. I've a few things bugging me about this design!

thanks again!