很奇怪的问题，救命啊！

C6416EMIFA的CE0空间接了一片32bit的SDRAM,C6416的高32bit悬空不用，在对SDRAM进行写操作时，对一个地址操作会同时影响与其相邻16byte的地址空间，如对0x8000 0000写数据时，0x8000 0000和0x8000 0010的数据都会改变，同时对0x8000 0010操作也会改变0x8000 0000的数据，请问这是怎么一回事啊?

我仔细查了下硬件，数据线、地址线都没有问题，数据类型定义为Unsigned int。而且如果用16bit的SDRAM，数据类型相应的改为Unsigned short时，此时相互影响的为每相隔8Byte的地址，如写数据到0x8000 0000，会使0x8000 0008内数据改变，反之也是。如果用8bit的SDRAM，相互影响的是0x8000 0000和0x8000 0004。这个是否与字节对齐有关?

怀疑是EMIFA的配置问题，
EMIFA的配置为：

static EMIFA_Config MyEmifaConfig =
{
EMIFA_GBLCTL_RMK
(
EMIFA_GBLCTL_EK2RATE_FULLCLK,
EMIFA_GBLCTL_EK2HZ_CLK,
EMIFA_GBLCTL_EK2EN_ENABLE,
EMIFA_GBLCTL_BRMODE_MRSTATUS,
EMIFA_GBLCTL_NOHOLD_DISABLE,
EMIFA_GBLCTL_EK1HZ_CLK,
EMIFA_GBLCTL_EK1EN_ENABLE,
EMIFA_GBLCTL_CLK4EN_ENABLE,
EMIFA_GBLCTL_CLK6EN_ENABLE
),
0xffffff33, //32BIT SDRAM
0xffffff13,
0xffffff13,
0xffffff13,
EMIFA_SDCTL_RMK
(
EMIFA_SDCTL_SDBSZ_4BANKS,
EMIFA_SDCTL_SDRSZ_12ROW,
EMIFA_SDCTL_SDCSZ_8COL,
EMIFA_SDCTL_RFEN_ENABLE,
EMIFA_SDCTL_INIT_YES, //SDRAM 配置完每个CE空间后，初始化
EMIFA_SDCTL_TRCD_OF(1), //TRCD = 20ns
EMIFA_SDCTL_TRP_OF(1), //TRP = 20ns
EMIFA_SDCTL_TRC_OF(6),
EMIFA_SDCTL_SLFRFR_DISABLE //self refresh mode disable
),
EMIFA_SDTIM_RMK
(
EMIFA_SDTIM_XRFR_DEFAULT, //EXT TIMER default
EMIFA_SDTIM_PERIOD_OF(1560) //64ms, 4096 cycle refresh
),
EMIFA_SDEXT_RMK
(
EMIFA_SDEXT_WR2RD_OF(0), //cycles between write to read command = 1 CLK
EMIFA_SDEXT_WR2DEAC_OF(1), //cycles between write to precharge
EMIFA_SDEXT_WR2WR_OF(0), //cycles between write to write = 1 CLK
EMIFA_SDEXT_R2WDQM_OF(1), //cycles between read to bex = 2 CLK
EMIFA_SDEXT_RD2WR_OF(0), //cycles between read to write = 1 CLK
EMIFA_SDEXT_RD2DEAC_OF(1), //cycles between read to precharge
EMIFA_SDEXT_RD2RD_OF(0), //cycles between read to read = 1 CLK
EMIFA_SDEXT_THZP_OF(0), //Troh = 2 CLK
EMIFA_SDEXT_TWR_OF(1), //Twr >= 1 CLK +7 ns
EMIFA_SDEXT_TRRD_OF(0), //Trrd >= 14ns
EMIFA_SDEXT_TRAS_OF(4), //Tras >= 42ns
EMIFA_SDEXT_TCL_OF(0) //cas latency = 2 CLK
),
0x00000002,
0x00000002,
0x00000002,
0x00000002
};

SDRAM时钟为100M，使用的是MT48LC4M32b2-7，1M*4BAMK*32bit，自己实在看不出什么问题，麻烦大家帮我看看。