SAR ADC Design Problem
I have a problem in design of SAR ADC. On its DC transfer C/Cs, the DC input signal (straightline) does not pass on the center of output steps (stair case) also some steps have different widths than the fixed step width.
Also this DC transfer C / Cs is shifted from ideal ADC transfer C / Cs (from Simulink).
Hint: I use charge redistribution SAR ADC architecture.
Thanks in advance
Pls post your architecture, your simulation conditions and simulation waveforms.
If it is a real circuit that you are mentioning,simulation and manufactured parts results all the complaints you have mentioned due to imperfections (matching, offset, linearity etc.i.e. a real ADC is never have a perfect offset, DNL and INL).
如果是，你提的一个实际电路，仿真和制造的部件导致各种你所提到的，由于缺陷的投诉（匹配，偏移，线性度等，也就是一个真正的ADC是永远不会有一个完美的偏移，DNL和INL）。
Thanks for your reply all
This results based on simulation not measurement in all typical typical conditions (so DNL/INL should not be appear between output from circuit and output from ideal ADC). As I mentioned I used the charge redistribution architecture which is consisted of charge redistribution DAC, comparator, and SAR logic.
xuexi
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SAR ADC Design Problem