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后仿真netlist error 问题

时间:10-02 整理:3721RD 点击:
DRC LVS均通过,PEX提参数0 error 0 warning但是进行后仿真时提示calibre view不存在,如下
ERROR (OSSHNL-108): The property, 'connectivityLastUpdated', specified on library 'ADPLL_layout', cell 'var_corase_bank_with_driver',
view 'calibre', does not have an integer value. Re-extract the design (File->Check
and Save menu option) to correct this error.
End netlisting Dec 23 16:41:58 2014
ERROR (OSSHNL-514): Netlist generation failed because of the errors reported above. The netlist might not have been generated at all or,if a netlist was produced, it might be corrupt.Fix the reported errors and generate the netlist again.
...unsuccessful
然后进入calibre view ,check & save 后显示提取出的电路有错,有电容short到了管子的漏极,如下所示:
ERROR (OSSHNL-514): Netlist generation failed because of the errors reported above. The netlist might not have been generated at all or,if a netlist was produced, it might be corrupt.Fix the reported errors and generate the netlist again.
...unsuccessful.
INFO (SCH-1170): Extracting "var_corase_bank_with_driver calibre"
Error: Net "c_43627_p" shorted to net "I6_I1_I2_MPM1@6_d".
Error: Net "c_43627_p" shorted to net "I6_I1_I2_MPM1@6_d".
Error: Net "I6_I1_I7_MPM1@2_d" shorted to net "c_50599_p".
Error: Net "I6_I1_I4_MPM1@9_d" shorted to net "c_13165_p".
Error: Net "c_13165_p" shorted to net "I6_I1_I4_MPM1@9_d".
Error: Net "c_50599_p" shorted to net "I6_I1_I7_MPM1@2_d".

发现问题了,PEX提出的netlist没有问题,mapping的时候place器件的时候有几个电容和MOS的terminal短路了,准备尝试place array看能否避免这种问题。
当然,mapping出来短路的原因还是没有找到

建议换一种后仿方法

有没有推荐的?

2013版本遇到这个问题,后来换成2014.4问题解决了

我遇到的这种情况,一种直接在Calibre 中把连接关系找出来,一般是器件和寄生器件叠在了一起,手动改。还有一种直接用CDL网表导入。

请问这个问题解决了么?

短路的原因找到了吗

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