verilog-A求助~~~~

最近再用verilog hdl建模，下面是一个电流控制电压源，里面加了些参数，保存时系统总报错，请大侠指教
`include "discipline.h"
`include "constants.h"
// $Date: 2017/02/13 08:46:22 $
// $Revision: 1.1 $
//
//
// Based on the OVI Verilog-A Language Reference Manual, version 1.0 1996
//
//

//--------------------
// ccvs_vh
//
// -current controlled voltage source for hall plate
//
// vout_p,vout_n:
controlled voltage terminals[V,A]
// iin_p,iin_n:
controlling current terminals [V,A]
//
// INSTANCE parameters
//rm = resistance multiplier (V to I gain) [Ohms]
//un = electrical mobility [m/V*s]
//r_H = hall factor []
//B = magnetic flux density [T]
//w = cross finger width [um]
//l = cross finger length [um]
//q = electrical charge of one electron [C]
//Ndnw = nwell doping concentration [m^-3]
//teff = effective depth of hall_plate [m]
//
// MODEL parameters
//{none}
//
module ccvs_vh(vout_p, vout_n, iin_p, iin_n);
input iin_p, iin_n;
output vout_p, vout_n;
electrical vout_p, vout_n, iin_p, iin_n;
parameter real teff = 5E-6;
parameter real Ndnw = 9E21;
parameter real q = 1.6E-19;
parameter real l = 20E-6;
parameter real w = 15E-6;
parameter real B = 0.1;
parameter real un = 0.046;
real r_H,theta_H,G,SI;

analog
r_H = 1/(q*Ndnw)
theta_H = atan(un*r_H*B)
G = 1-5.0267*theta_H/tan(theta_H)*E-(`M_PI*(w+2*l)/(2*w))
SI = G*r_H/(q*Ndwn*teff)
V(vout_p, vout_n) <+ 0.5*SI*I(iin_p, iin_n)*B;

endmodule

试试在每个表达式语句后面加上结束的分号“；”

已get,谢谢