關於利用Verilog-A 模擬ADC的錯誤
时间：10-02
整理：3721RD
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您好
使用Verilog-A 跑 behavior model的時候 有一些狀況
V(out) <+ transition(result, td, tt);//tt=rise time
這一行老是會出錯不知原因是什麼
錯誤訊息如下
hsp-vacomp: Error: Vector access index for 'out' must be invariant or within an unrolled genvar loop.
懇請各位分享了
版本為 2009.0 Hspice
下面是完整的code
/////////N-bit Analg to Digital Converter///////////
module adc(out, in, clk);
parameter integer bits=8 from[1:30];
// resolution (bits)
parameter real
fullscale
=
1.0;
//input rage is from 0 to fullscale (V)
parameter real
td
=
0;
//delay from clock edge to output (s)
parameter real
tt
=
0;
//transition time
parameter real
vdd
= 5.0;
//voltage level of logic 1 (V)
parameter real
thresh
=
vdd/2;
//logic threshold level (V)
parameter integer
dir
=
1
from[-1:1]
exclude 0;
//1 for rising edges,-1 for falling
input
in,
clk;
output
[0:bits-1] out;
//output
out;
voltage
in, clk;
voltage
[0:bits-1] out;//out[0],
out[1],
out[2], ... ,out[bit-1]
//voltage
out;
real
sample, midpoint;
integer
result[0:bits-1];//result[0], result[1] ...
genvar
i;
// define "i" for loop
analog
begin
@(cross(V(clk)-thresh,+1) or initial_step)
begin
sample = V(in);
midpoint = fullscale/2.0;
for (i=bits-1;
i>=0;
i=i-1)
begin
if (sample > midpoint)
begin
result=vdd;
sample=sample-midpoint;
end
else
begin
result=0.0;
end
end
sample = 2.0*sample;
end
for(i=0;
i<bits;
i=i+1) begin
V(out) <+ transition(result, td, tt);//tt=rise time
end
end
endmodule
///////////////////////
/// 錯誤資訊///
hsp-vacomp: Warning: Unable to unroll genvar loop: loop bounds not constant at compile time.
hsp-vacomp:
['behavior_model.va',488]
hsp-vacomp: Warning: Unable to unroll genvar loop: loop bounds not constant at compile time.
hsp-vacomp:
['behavior_model.va',502]
hsp-vacomp: Error: Vector access index for 'out' must be invariant or within an unrolled genvar loop.
hsp-vacomp:
['behavior_model.va',503]
** error **
During Verilog-A Device processing:
Failed to compile the Verilog-A File,
'g:\hspice_sim\veriloga\behavior_va\behavior_model.va'.
lic: Release hspice token(s)
/// 錯誤資訊///
使用Verilog-A 跑 behavior model的時候 有一些狀況
V(out) <+ transition(result, td, tt);//tt=rise time
這一行老是會出錯不知原因是什麼
錯誤訊息如下
hsp-vacomp: Error: Vector access index for 'out' must be invariant or within an unrolled genvar loop.
懇請各位分享了
版本為 2009.0 Hspice
下面是完整的code
/////////N-bit Analg to Digital Converter///////////
module adc(out, in, clk);
parameter integer bits=8 from[1:30];
// resolution (bits)
parameter real
fullscale
=
1.0;
//input rage is from 0 to fullscale (V)
parameter real
td
=
0;
//delay from clock edge to output (s)
parameter real
tt
=
0;
//transition time
parameter real
vdd
= 5.0;
//voltage level of logic 1 (V)
parameter real
thresh
=
vdd/2;
//logic threshold level (V)
parameter integer
dir
=
1
from[-1:1]
exclude 0;
//1 for rising edges,-1 for falling
input
in,
clk;
output
[0:bits-1] out;
//output
out;
voltage
in, clk;
voltage
[0:bits-1] out;//out[0],
out[1],
out[2], ... ,out[bit-1]
//voltage
out;
real
sample, midpoint;
integer
result[0:bits-1];//result[0], result[1] ...
genvar
i;
// define "i" for loop
analog
begin
@(cross(V(clk)-thresh,+1) or initial_step)
begin
sample = V(in);
midpoint = fullscale/2.0;
for (i=bits-1;
i>=0;
i=i-1)
begin
if (sample > midpoint)
begin
result=vdd;
sample=sample-midpoint;
end
else
begin
result=0.0;
end
end
sample = 2.0*sample;
end
for(i=0;
i<bits;
i=i+1) begin
V(out) <+ transition(result, td, tt);//tt=rise time
end
end
endmodule
///////////////////////
/// 錯誤資訊///
hsp-vacomp: Warning: Unable to unroll genvar loop: loop bounds not constant at compile time.
hsp-vacomp:
['behavior_model.va',488]
hsp-vacomp: Warning: Unable to unroll genvar loop: loop bounds not constant at compile time.
hsp-vacomp:
['behavior_model.va',502]
hsp-vacomp: Error: Vector access index for 'out' must be invariant or within an unrolled genvar loop.
hsp-vacomp:
['behavior_model.va',503]
** error **
During Verilog-A Device processing:
Failed to compile the Verilog-A File,
'g:\hspice_sim\veriloga\behavior_va\behavior_model.va'.
lic: Release hspice token(s)
/// 錯誤資訊///
申明部分把 out 和 result 都声明为向量，为何下标没了?
您好 感謝你的回覆請問可否有建議寫法?
我以為像是 V(in)這樣 不用額外再寫些什麼
就可以跑了
verilog-a 菜鳥 麻煩多多教導了
我们走得太快，灵魂都跟不上了。
哥你這個回答我的靈魂也追不上了 QQ
hsp-vacomp: Error: Vector access index for 'out' must be invariant or within an unrolled genvar loop.
有沒有人碰過這個錯誤阿~
BUS信号的宽度应该不能用parameter 定义，所以才会出错