pll相噪建模，怎样定义端口类型为相位类型呢

Phase-domain VCO noise model.
‘include “discipline.h”
`include “constants.h”
module vco(in, out);
input in; output out;
voltage in;
phase out;
parameter real gain = 1 from (0:inf); // transfer gain, Kvco (Hz/V)
parameter real n = 0 from [0:inf); // white output phase noise at 1 Hz (rad2/Hz)
parameter real fc = 0 from [0:inf); // flicker noise corner frequency (Hz)
analog begin
Theta(out) <+ 2∗`M_PI∗gain∗idt(V(in));
Theta(out) <+ flicker_noise(n, 2, “wpn”) + flicker_noise(n∗fc, 3, “fpn”);
end
endmodule
在Ken Kundert的文档《Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers》中，对vco等模块的建模都使用了phase端口类型来定义一个相位端口，而我在cadence中，提示语法错误
Error found by spectre during AHDL compile.
ERROR (VACOMP-2259): "phase out<<--? ;"
"/home/zhuchaoyong15/work/PLL_SY/vco/veriloga/veriloga.va", line 9:
syntax error.
ERROR (VACOMP-1814): Maximum allowable errors exceeded. Exiting AHDL
compilation...
而且在cadence的帮助文档找不到phase这种类型的端口定义，特别是flicker_noise 和white_noise的函数说明中也表示，函数是电压电流的参量
5 white_noise
White noise expression. Valid for v and i elements.
6 flicker_noise
Flicker noise expression. Valid for v and i elements.

求路过大神佐证，vco模块的相位端口建模是不是真的在cadence中不行

坐等大神指点