.def文件如何转换成Verilog-A文件
时间：10-02
整理：3721RD
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仿真出现错误：
FATAL (VACOMP-2096): File '/home/Cadence/../models/spectre/res.def' does not appear to be a valid Verilog-A file. In previous releases, '.def' was a file extension typically used for SpectreHDL files but SpectreHDL is no longer supported. If this file is a SpectreHDL file, you need to replace it with an equivalent Verilog-A file.
目前没有替代文件可用，.def文件能否直接转换成Verilog-A文件呢，可以的话转换成什么格式?或者用Verilog-A语言重新描述一遍?请指点
用的MMSIM7.2
FATAL (VACOMP-2096): File '/home/Cadence/../models/spectre/res.def' does not appear to be a valid Verilog-A file. In previous releases, '.def' was a file extension typically used for SpectreHDL files but SpectreHDL is no longer supported. If this file is a SpectreHDL file, you need to replace it with an equivalent Verilog-A file.
目前没有替代文件可用，.def文件能否直接转换成Verilog-A文件呢，可以的话转换成什么格式?或者用Verilog-A语言重新描述一遍?请指点
用的MMSIM7.2
大虾不吝赐教啊，表示十分捉急。
我的问题太低端了么。
再来顶贴
请问你的问题解决了吗
去厂家要了一个.va文件代替.def就可以了。
解决方案：
http://bbs.eetop.cn/viewthread.php?tid=393251