新手求助Hspice仿真问题

error信息看的不全

1. ****** HSPICE -- J-2014.09-SP2 64-BIT (Feb 26 2015) RHEL64 ******
   
2. Copyright (C) 2014 Synopsys, Inc. All Rights Reserved.
   
3. Unpublished-rights reserved under US copyright laws.
   
4. This program is protected by law and is subject to the
   
5. terms and conditions of the license agreement from Synopsys.
   
6. Use of this program is your acceptance to be bound by the
   
7. license agreement. HSPICE is the trademark of Synopsys, Inc.
   
8. Input File: s38417_trojan1.spf
   
9. Command line options: s38417_trojan1.spf
   
10. lic:
    
11. lic:
    
12. lic:
    
13. lic:
    
14. lic:
    
15. lic:
    
16. lic:
    
17. lic:
    
18. lic:
    
19. lic:
    
20. Init: read install configuration file: /root/simulation/install_path/synopsys/hs/hspice/meta.cfg
    
21. **error** (s38417_trojan1.spf:490100)Extra numerical data on above linetoken number=36
    
22. **error** (s38417_trojan1.spf:490100) difficulty in reading input
    
23. 
    
24. ***** job aborted
    
25. 1****** HSPICE -- J-2014.09-SP2 64-BIT (Feb 26 2015) RHEL64 ******
    
26. ******
    
27. .title s38417_trojan1
    
28. 
    
29. ****** job statistics summary tnom=25.000 temp=25.000 ******
    
30. 
    
31. 
    
32. ******Machine Information******
    
33. CPU:
    
34. model name: Intel(R) Xeon(R) CPU E5-2650 v3 @ 2.30GHz
    
35. cpu MHz: 2301.000
    
36. 
    
37. OS:
    
38. Linux version 2.6.32-573.22.1.el6.x86_64 (mockbuild@c6b8.bsys.dev.centos.org) (gcc version 4.4.7 20120313 (Red Hat 4.4.7-16) (GCC) ) #1 SMP Wed Mar 23 03:35:39 UTC 2016
    
39. 
    
40. 
    
41. ******HSPICE Threads Information******
    
42. 
    
43. Command Line Threads Count :1
    
44. Available CPU Count:40
    
45. Actual Threads Count:1
    
46. 
    
47. 
    
48. ******Circuit Statistics******
    
49. # nodes=0 # elements=296622
    
50. # resistors=180603 # capacitors =116019 # inductors=0
    
51. # mutual_inds =0 # vccs=0 # vcvs=0
    
52. # cccs=0 # ccvs=0 # volt_srcs=0
    
53. # curr_srcs=0 # diodes=0 # bjts=0
    
54. # jfets=0 # mosfets=0 # U elements=0
    
55. # T elements=0 # W elements =0 # B elements=0
    
56. # S elements=0 # P elements =0 # va device=0
    
57. # vector_srcs =0 # N elements =0
    
58. 
    
59. 
    
60. ******Runtime Statistics (seconds)******
    
61. 
    
62. analysistime# pointstot. iterconv.iter
    
63. op point0.0010
    
64. readin10.38
    
65. errchk0.00
    
66. setup0.00
    
67. output0.00
    
68. 
    
69. 
    
70. peak memory used1294.95 megabytes
    
71. total cpu time10.78 seconds
    
72. total elapsed time11.65 seconds
    
73. job started at15:27:51 04/18/2016
    
74. job endedat15:28:03 04/18/2016
    
75. 
    
76. 
    
77. 
    
78. >error***** hspice job aborted
    
79. lic: Release hspice token(s)
    
80. lic: total license checkout elapse time:0.38(s)

给大家说一下我面临的难题。
毕设，我修改了一个verilog标准电路，综合得到的verilog网表，老师想看到修改过的电路电源电压的波形和原标准电路电源电压波形有无差别，就让我用Hspice仿真。
师兄让我用IC Compiler把verilog网表输出为def文件，再用StarRC抽取为spef网表，自己加入数字激励，进行Hspice仿真。
我感觉是我的spef网表有问题，因为StarRC抽取的只是寄生参数网表。
逻辑结构被忽略，是否成为了我对spef网表进行仿真时频频报错的原因?
希望有好心的大神帮帮我这个菜鸟本科生，解答一下让我知道问题出在哪，我做了将近一个星期这个仿真结果还是没出来，卡得我太难受了。

这个网表是有问题的：在hspice里面是有意义的 不能代表端口

问题解决了，网表有问题，starRC抽取的spf文件里面好多节点标号都出现了\[0\] \[1\] \[...\]这样的格式，把它修改为[0]就可以了