vccap的使用
时间:10-02
整理:3721RD
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仿真时使用一个电压源来控制改变一个电容的实时值,但是在仿真生成网表时出现以下错误,请大虾门指点指点
ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'spectre cmos_sch cmos.sch schematic veriloga', for the
instance 'G0' in cell 'Cfenya'. Either add one of these views to the library 'analogLib',
cell 'vccap' or modify the view list to contain an existing view.
cadence版本 ic615,mmsim13
电路如下
ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'spectre cmos_sch cmos.sch schematic veriloga', for the
instance 'G0' in cell 'Cfenya'. Either add one of these views to the library 'analogLib',
cell 'vccap' or modify the view list to contain an existing view.
cadence版本 ic615,mmsim13
电路如下
![](../imgqa/etop/rfic/rfic-5150xkpm53qbuqg.png)
已解决,参考cadence support的方案,使用VCCS,把typeof source修改成vccap,就可以当成电压控电容用了。
可以使用sprctre -h vccs查看详情
不过,直接调用vccap不知道为啥不能用,还是希望有懂得人解答一下呢。