用plllib里的模块搭建了PLL行为级,并进行仿真,仿真遇到error:“/home/APP/cadence/...../plllib/divider_volt_domain/veriloga/veriloga.va” line 50:encountered an undefined function bound_step.check the spelling of the fuctin or define te function before using it. 我打开veriloga.va后,发现里面的bound_step函数并没有被注释掉。bound_step(0.05*divide_r/(fout+1)); 接下来不知道怎么办,,求帮助~