hspice仿真出现no data in design。

小弟初学者~
什么原因啊?
怎么解决呢?
谢谢~

附网表文件：
zuoye3
.inc 'E:\VLSI zuoye\mos18.mod'
.option list node nomod
.global vdd
.param cbit=0.5p cdl=0.2p vddd=1.8 lm=0.18u
.lib 'E:\VLSI zuoye\ms018_model\ms018_v1p8.lib'tt
.tran 0.01n 50n
.meas tran td trig v(se) val=0.6 rise=2 targ v(dout)
val=0.6 fall=1
vdd vdd 0 vddd
vwt wt 0 pulse(0 vddd 0 0 0 10n 20n)
vwtbar wtbar 0 pulse(vddd 0 0 0 0 10n 20n)
vdin din 0 pulse(0 vddd 0 0 0 20n 40n)
vpre pre 0 pulse(0 vddd 2.5n 0 0 7.5n 10n)
vrow row 0 pulse(0 vddd 2.5n 0 0 5n 10n)
vcol col 0 pulse(0 vddd 2.5n 0 0 5n 10n)
vcolbar colbar 0 pulse(vddd 0 2.5n 0 0 5n 10n)
vse se 0 pulse(0 vddd 13.5n 0 0 4n 20n)
.subckt inverter in out
mp out in vdd vdd pmos18 w='12*lm' l=lm
mn out in 0 0 nmos18 w='4*lm' l=lm
.ends inverter
.subckt trans ctrl ctrlbar in out
mp out ctrlbar in vdd pmos18 w='12*lm' l=lm
mn out ctrl in 0 nmos18 w='4*lm' l=lm
.ends trans
.subckt tri ctrl ctrlbar in out
Xinverter in dummy inverter
Xtrans ctrl ctrlbar dummy out trans
.ends tri
.subckt cell wline bit bitbar
mp1 data1 data2 vdd vdd pmos18 w='1.6*lm' l=lm
mp2 data2 data1 vdd vdd pmos18 w='1.6*lm' l=lm
mn1 data1 data2 0 0 nmos18 w='1.6*lm' l=lm
mn2 data2 data1 0 0 nmos18 w='1.6*lm' l=lm
mgate1 bitbar wline data1 0 nmos18 w='2*lm' l=lm
mgate2 bit wline data2 0 nmos18 w='2*lm' l=lm
.ends cell
.subckt sa se dl dlbar dout doutbar
mpre1 dout se vdd vdd pmos18 w='4*lm' l=lm
mpre2 doutbar se vdd vdd pmos18 w='4*lm' l=lm
mp1 dout doutbar vdd vdd pmos18 w='12*lm' l=lm
mp2 doutbar dout vdd vdd pmos18 w='12*lm' l=lm
mn1 dout doutbar dummy1 0 nmos18 w='8*lm' l=lm
mn2 doutbar dout dummy2 0 nmos18 w='8*lm' l=lm
min1 dummy1 dl dummy3 0 nmos18 w='8*lm' l=lm
min2 dummy2 dlbar dummy3 0 nmos18 w='8*lm' l=lm
mtail dummy3 se 0 0 nmos18 w='12*lm' l=lm
.ends sa
mpre1 bitbar pre vdd vdd pmos18 w='4*lm' l=lm
mpre2 bit pre vdd vdd pmos18 w='4*lm' l=lm
Xcell row bit bitbar cell
Cbit1 bitbar 0 cbit
Cbit2 bit 0 cbit
Xtrans1 col colbar bitbar dl trans
Xtrans2 col colbar bit dlbar trans
mpre3 dl pre vdd vdd pmos18 w='4*lm' l=lm
mpre4 dlbar pre vdd vdd pmos18 w='4*lm' l=lm
Cdl1 dl 0 cdl
Cdl2 dlbar 0 cdl
Xtri1 wt wtbar din dl tri
Xtri2 wt wtbar d_dummy dlbar tri
Xinverter din d_dummy inverter
Xsa se dl dlbar dout doutbar sa
.end

大家都没这个问题吗?

是不是打开波形文件时出现的这个提示?

是的，不知道哪里出错了。

加上
.option post试试

**error** model name pmos18 in the element0:mpre1
is not defined.
***** job aborted

这是什么错误?

查查你调用的model里对PMOS的描述，是pmos18么?
另外这一句
vdd vdd 0 vddd
好象你没给出所加电源的值吧，1.8V的电源?那应写成
vdd vdd 0 1.8

老办法，一句一句的屏蔽，直至精简到最简单的网表

十分感谢，mod...里果然不是pmos18！呵呵~

你的网表里面没有输出波形，所以看波形的时候没有数据。
加上.probe/.print v(xx)问题就解决了

同问。