运放环路稳定性的仿真如何来选取断开环路的地方

depends on how many loops you have and which loop you are interested in

同问，希望一起讨论讨论，断点处不一样，AC特性可能不一样，应该有个比较common的断点

这是个很重要的问题，但这方面的讨论太少
最重要的是断开的地方要是总的环路，很多电路都不只是一个环路。还有断开处要考虑负载的影响，比如选择的断开点是两级运放的中间，那么断开环路的末端是第一级运放输出，则应该挂上第二级。请各位指正。~

有意思下回注意一下

gate之前，输入高阻的地方。

Hi all:
Connect as a unit gain buffer and cut the feedback.
If I have any mistake, please correct me.
mpig

the loop may be broken anywhere. But it is convenient to do so right at an ideal voltage or current source so that the equivalent terminating impedance plays no role in the results.