LDO负载电流为3A时,交流仿真为什么是这样?如何改进
时间:10-02
整理:3721RD
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增益怎么变成这样,怎么从负的开始,如何分析,电路改怎么改进
Hi Apenper:
If the output cap has a ESR, the LDO is 2 pole and 1 zero system.
At the heavy load, one pole is higher than the zero and other is
closed to low frequency the result is like your picture.
If your compensation is based on an external element (Cout + ESR),
I suggest the zero is in the LDO.
mpig
是负载电流过大,LDO已经进入by-pass状态了么
谢谢正如上面所说负载电流过大问题已经解决
请问什么是bypass状态呢,是指管子进入线性区么?