Dual loop CDR (clock data recovery) used in high speed transceiver

Hi, i am currently working on dual loop CDR design architecture used in the high speed transceiver. Mostly of the time, i am referring to the IEEE paper but hardly to understand all maybe i am still a beginner to CDR design. Can somehow show me where can i download a good reference book discussing about CDR? One more thing to ask is that what will make the chip to have high bit error rate?

I am also searching this topic. Please tell me if you get any information.

me too ,thank you！

so far no response

KAN KAN

Reply 1 # kkliaw77

Needgodfatherhelp