250MHz 10bit ADC进展与求助
做整个pipelineADC的simualtion，但是没有包括参考电压产生电路
目前给的是理想的参考电压
目前完成的电路主要包括：时钟产生电路，digital correction部分，
还有pipeline的S/H级和各个stage ，每个stage里面有MDAC和subADC，subADC主要是comparator
MDAC里面是gain=2的switch capcitor 和 opamp。
整个ADC共9级
S/H + ST1 + ST2 + ST3 + ... + ST8 + ST9
其中第三级到第八级目前用的相同的，
整个simualtion 跑下来，结果不是很理想
输入信号Vdiff= +/- 0.5V（满幅），
结果是 HD3 = -62.4dB; HD5 = -68.8dB总的THD= 0.119%
感觉稍微差了点，而且非常疑惑
每一级都做过simualtion，而且感觉非常理想
S/H：HD3=-93.5dB； THD=0.0033%约-89dB, 这而且是从整个ADCTOP 仿真中，S/H输出接到下一级Stage1的地方抽
出来做DFT的，所以THD 变差因该是后级电路引起的
STAGE1：把做加减vrefp vrefn的电路去掉，纯粹做gain=2的瞬态仿真，再作DFT，结果很好，也有90多dB,于是想会不会是因为做了电压加减法，导致THD变差，于是输入一个DC-level偏高的sin信号，让MDAC一直做减法，减掉一个VREFP，输出还是一个sin信号，只是电压向下平移了，DFT分析HD3=-96dB, THD=0.0031%
STAGE2：也像stage1 一样做了纯粹乘2和减vref的仿真，HD3=-100dB，THD=0.003%。
STAGE3：也像stage1一样的，结果也不差
好像找不出合在一起就变差的理由啊，郁闷啊
在这之前ADC的stage7 stage8 的opamp没有用gain boost结构，第一级MDAC的opamp与SH的一样，
结果是整个ADC的HD3=-58.5dB，后来增加了MDAC1的带宽，把第七第八级弄得和STAGE3一样
得到现在的结果只改进了大概4dB
What input do u use?
Hi,
Your question is very interesting. I'd like to ask you what input did you use to measure your HD3 and THD?
Also, in stage 4 and below, do you use the same size of switches as stage 1-3? If you scaled switches too aggresive, it reduced your HD3 too.
Let me know if that helps.
ps: I can read Chinese but can't type in this computer.
我用的单频sin信号输入，也有人说要用two tone sinwave input，那样更能看出谐波失真和两个频率之间的调制出的差频。
every stage scaling down，我是按照80%scaling down的，即后级是前级80%
但是我的switches 还没有做scaling down，我是想先跑出个整体特性，再每级做power optimization
Sub_ADC产生的glitch怎么样?看过没有?时钟搭配要合理,当然开关的谐波要设计得合理.输入的信号频率与采样频率要有一定的关系,才会得到最差情况下的谐波.
十分感谢
可是按照非相干采样，输入信号有特殊的要求
现在采样时钟250MHz，输入信号9.0332MHz的sin
要去一个质数去算出一个输入频率，但是这个频率肯定不会与clk成倍数关系啊，
什么情况下才会得到最差谐波啊
你单测mdac 的时候怎么测的?
就是连成一个gain =2 的amp 用sine测?
如果sine 频率太低，要比实际上的mdac 要慢多了
mdac 是可以见到fs/2 的信号的。
你试试看，用fs/2 的正弦波来测试，看看是不是还是90+ THD
你做了多少点DFT?
做1024点的DFT啊，基本上要2天时间，由于是仿真，做不了太多的DFT
但因该差不多可以看出THD的基本特性了吧
到最后会跑一个较长的simulation做个4096点的DFT
您的建议台有价值了，我突然想起来，在S/H电路中
输入频率124.3MHz的时候，SFDR才-67.7dB，都是比124.3MHz低一点的频率，因该是高频折进来的
输入信号接近奈奎斯特频率的时候THD肯定会变差么
这时候的THD因该主要来自于采样开关的的电阻非线性导致的吧，因为opamp的stettling还是从VCM到某个值的
那我应该要减小开关的电阻咯，试试
可以在S/H采样电容前 也就是采样开关后，放个百ohm左右（具体大小根据你的开关等效电阻来）的小电阻，这样的话可以将两边开关的非线性减少到最小值
单纯的减少开关的电阻 所带来的电荷注入效应对采样电容的影响还是蛮大的。
而且 考虑到版图 这两个小电阻最好用低方块值的电阻（非硅化的，而且受电压影响小的，具体选择参考一下这种process的design rule）
哦，不过突然想到，过了S/H后的信号已经不是连续信号了啊
所以后级因该市settling的问题吧，settle 的精度到了就因该满足要求的
就是需要settle 的信号的值 变化的更快
就说你的SH怎么那么好呢，原理输入信号频率低。跑跑输入信号频率为250M*1023/2048=124.8779296875M的单端信号，2048个点的FFT。这个应该是最极端情况。
MDAC 的输出不是连续信号，所以要求更高的slew rate
这种情况跑过啊，SFDR是-68dB吧
跑了一下输入124.7559MHz的输入
第一级MDAC的 SFDR = -95dB
第二级MDAC的 SFDR = -97dB
第三级MDAC的 SFDR = -92dB
哦，输入满幅应该是+/-0.5V，
现在输入是+/-0.15V，是为了给输入信号加一个DC offset， 让MDAC一直做减法，
要测满幅的就要把subADC和控制电路去掉，单独测gain=2的特性
just curious, what kind of process r u using to design the 250M 10 bit ADC? r u using multi channels or a single channel? what is ur supply voltage?
65nm process, signle channel only with digital correction instead of digital calibration
power supply 1.1V
another question,why are u using 1024 points to do the DFT while 16, 32 points is enough to test your ckts' THD?
纯顶贴，请问lz用的 op amp是什么样的结构，我现在用folded-cascode作不了那么大的带宽（只有600Mhz的 GBW），而且功耗很大（6mA），90nm/1.0V
more points to do DFT analysis, more accuracy spectrum you will get
for example
if you do 1024 points DFT for 250MHz sample clk, the adjacent two frequency different is 250M/1024=244KHz
if you do 32 points DFT for 250MHz sample clk, the adjacent two frequency different is 250M/32=7.8MHz
the more points DFT, the higher resolution you'll get
just folded cascode?
what is your swing requirement?
yeah, 1024 points can have more resolution though,
but, if you can find problems by using 16 points, why bother 1024 points in the first place. You can save a lot of time using 16, 32 points.
BTW, your THD results is too good for a 10 bit ADC. are u using real switches or ideal switches? real CMFB or ideal CMFB?
swithes and CMFB are real devices
only Vref and VCM are ideal
I can not find problems
You can use your switch with an ideal opamp and see how much THD you can get.
btw, what architeture of opamp do u use and how much UGBW for your first stage opamp?
gainboost opamp open loop gain is about 83dB,
S/H opamp UGBW is about 1.1GHz
s/h 结构?
Here are some comments:
1. UGB=1.1Ghz is not enough for 250Mhz 10bit.The THD degradation is most likely due to too low UGB
For some margin, UGB=2Ghzat least
2. Using coherence sampling always, 1024 bit is enough for FFT. However, pls check S/H first with your first stage MDAC loading. Plot FFT of S/H output see if your THD meets.
3. What kind of 65nm you are using, G or LP, there are a lot of diference. If you are design at VDDA=1.1V, pls check with VDDA=1.2V see if yor THD improve or not.
4. Can you plot the Vres of each stage? Also check THD at 0dBFS for the OPA you are using.
5. Finally, if you have the ouptut data or waveforms, I can check for you.
Hopefully this will help you.
Thank you for your advice
1. UGB=1.1Ghz is not enough for 250Mhz 10bit.The THD degradation is most likely
due to too low UGB0
Becase of the sample hold is capacitor flip structure, its feedback factor is nearly 1.
The UGB=1.1GHz seems enough for 250MHz 10bit
2. Using coherence sampling always, 1024 bit is enough for FFT. However, pls check S/H first with your first stage MDAC loading. Plot FFT of S/H output see if your THD meets
S/H with loading test is OK. when the whole ADC circuit is connected together, run the top level simulation. Do 1024 DFT for the S/H outputsample signal(the connect point of S/H and MDAC1). It can reach -95dB SFDR
3 If you are design at VDDA=1.1V, pls check with VDDA=1.2V see if yor THD improve or not
65nm process VDD is 1.0V. I have already over stress power supply a little. If worry about output range is too large, a smaller signal can be forced in in stead of full scale signal.
4 Can you plot the Vres of each stage? Also check THD at 0dBFS for the OPA you are using
Yes, I have saved the Vres of each stage. The vres settling looks OK.
I don't know the meaning of "THD at 0dBFS for the OPA "
5. I can't cutsome picture on work station. But I print some picture on paper.
I really hope you give me some information
Thanks a lot
1. For 10bit, need about 7 tor. And Settling time=Ts/2=2ns, acutally only 1.8ns due to non-overlapped clock. For GBW=1.1Ghz, 7 tor about 7*1/(2*pi*GBW)=1.1ns<1.8ns, the rest 0.7ns can be use for slewing. If GBW=1.1Ghz is the worst case. It maybe fine for S&H.
However for MDAC, for 1.5bit/stage, it may be not. since now total 7/(2*pi*0.5*GBW)=2.2ns>1.8ns. It will harm your THD.
2. If your S/H is ok (-90dB below), why the whole simulation only -6xdB? Pls check Linearity of 1st MDAC using three point input signal to get corresponding three vres, then plot Vres vs Vin to see how linear it is. I believe, that will be the issue.
3. For 65nm 1V device can be stresss to 1.1V for sure. What I means is try to avoid large signal gain distortion for the OPA. This is why I ask you to try 1.2V. I am not going to ask you put your circuit work under 1.2V, only ask you to run simulation at 1.2V to see if the results get better
4. Another suggestion is pls pay attention when you check the FFT results. Using 1.111Mhz(cohenent to 250Mhz) input to check FFT see if better and calculate THD and compared with the standalone block. If ok, then increase input frequency and run again see where THD will degrade. If no change, then Gain is a suspicous issue and however, if degradation a lot, then BW is the factor instead.
Hopefully it helps you.