sigma-delta调制器中奇次项谐波的消除

First of all, you should know which part cause the odd-order distortion, OTA or DAC ?
The output DR of OTA is enough ? The input amp of your OTA is small ? GBW is large enough ?
If you use CIFF topology, the design of your summing block is good ?
The ELD compensation's timing is correct ?
4-bit will have a very high requirement on your DAC. The timing, overshoot, DWA.........

In addition, is your system level design is correct ? I found that some guys use z-domain model to simulation CT-DSM, that will cause a prolem. And your solver in simulink should be ode15s or 23s, not ode45, ode45 is for DT-DSM.

小编能详细解释一下ode23 ode45吗

ode45 is non-stiff solver. CT-DSM is stiff, ode23s and ode15s are stiff solvers. they are better.
You can use ode45, but you should use it carefully.

Thanks for banzhu's response

能不能展开说一下为啥CT sigma-delta adc 是 stiff ode?如果用ode45 有什么坏处?spice 是什么solver? stiff 还是non-stiff?

I forget the answer to the first question. I saw it in a PhD thesis, it says it's stiff.

Use ode45 is not efficient and may cause inaccurate instability.
In spectre, if you use "conservative", it's gear2only
ode15s use grear method, it use more equations in one step, but less steps than ode45, so it's more efficient

您讲到“If you use CIFF topology, the design of your summing block is good ?”
我想问设计summing block应该注意一些什么问题，以避免谐波的产生。
谢谢。

小编您好，您说到CIFF结构时，加法器部分必须仔细考虑。不知道我这样看对不对。比如说一个三阶一位量化CIFF结构，不包含输入信号前馈通路，积分器输出前馈系数为：a1,a2,a3。那我电路实现的时候，求和电容Ca1、Ca2、Ca3(他们的电容和为Ct) 则要满足如下关系式：1)、Ca1:Ca2:Ca3=a1:a2:a3。2)、根据电荷守恒又有：a1+a2+a3=Ca1/Ct + Ca2/Ct + Ca3/Ct =1，那么我在系统设计时，是否一定要做到a1+a2+a3=1呢，我看到实际上很多文献都没有这么做。其余需要考虑的是不是就是面积、匹配、功耗吧?

如果要得到C1, C2, C3的值，除了需要知道a1, a2, a3之外，还要知道Ct,
那么请问，您的Ct是怎样得到的呢?
谢谢。